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alx: remove WoL support
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Unfortunately, WoL is broken and the system will immediately
resume after suspending, and I can't seem to figure out why.
Remove WoL support until the issue can be found.

Signed-off-by: Johannes Berg <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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@jmberg @davem330
jmberg authored and davem330 committed Jul 3, 2013
1 parent 0c1072a commit bc2bebe
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Showing 4 changed files with 15 additions and 323 deletions.
36 changes: 0 additions & 36 deletions drivers/net/ethernet/atheros/alx/ethtool.c
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Original file line number Diff line number Diff line change
Expand Up @@ -201,48 +201,12 @@ static void alx_set_msglevel(struct net_device *netdev, u32 data)
alx->msg_enable = data;
}

static void alx_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
struct alx_priv *alx = netdev_priv(netdev);
struct alx_hw *hw = &alx->hw;

wol->supported = WAKE_MAGIC | WAKE_PHY;
wol->wolopts = 0;

if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
wol->wolopts |= WAKE_MAGIC;
if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY)
wol->wolopts |= WAKE_PHY;
}

static int alx_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
struct alx_priv *alx = netdev_priv(netdev);
struct alx_hw *hw = &alx->hw;

if (wol->wolopts & ~(WAKE_MAGIC | WAKE_PHY))
return -EOPNOTSUPP;

hw->sleep_ctrl = 0;

if (wol->wolopts & WAKE_MAGIC)
hw->sleep_ctrl |= ALX_SLEEP_WOL_MAGIC;
if (wol->wolopts & WAKE_PHY)
hw->sleep_ctrl |= ALX_SLEEP_WOL_PHY;

device_set_wakeup_enable(&alx->hw.pdev->dev, hw->sleep_ctrl);

return 0;
}

const struct ethtool_ops alx_ethtool_ops = {
.get_settings = alx_get_settings,
.set_settings = alx_set_settings,
.get_pauseparam = alx_get_pauseparam,
.set_pauseparam = alx_set_pauseparam,
.get_msglevel = alx_get_msglevel,
.set_msglevel = alx_set_msglevel,
.get_wol = alx_get_wol,
.set_wol = alx_set_wol,
.get_link = ethtool_op_get_link,
};
155 changes: 0 additions & 155 deletions drivers/net/ethernet/atheros/alx/hw.c
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Original file line number Diff line number Diff line change
Expand Up @@ -332,16 +332,6 @@ void alx_set_macaddr(struct alx_hw *hw, const u8 *addr)
alx_write_mem32(hw, ALX_STAD1, val);
}

static void alx_enable_osc(struct alx_hw *hw)
{
u32 val;

/* rising edge */
val = alx_read_mem32(hw, ALX_MISC);
alx_write_mem32(hw, ALX_MISC, val & ~ALX_MISC_INTNLOSC_OPEN);
alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
}

static void alx_reset_osc(struct alx_hw *hw, u8 rev)
{
u32 val, val2;
Expand Down Expand Up @@ -858,66 +848,6 @@ void alx_post_phy_link(struct alx_hw *hw)
}
}


/* NOTE:
* 1. phy link must be established before calling this function
* 2. wol option (pattern,magic,link,etc.) is configed before call it.
*/
int alx_pre_suspend(struct alx_hw *hw, int speed, u8 duplex)
{
u32 master, mac, phy, val;
int err = 0;

master = alx_read_mem32(hw, ALX_MASTER);
master &= ~ALX_MASTER_PCLKSEL_SRDS;
mac = hw->rx_ctrl;
/* 10/100 half */
ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED, ALX_MAC_CTRL_SPEED_10_100);
mac &= ~(ALX_MAC_CTRL_FULLD | ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN);

phy = alx_read_mem32(hw, ALX_PHY_CTRL);
phy &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_CLS);
phy |= ALX_PHY_CTRL_RST_ANALOG | ALX_PHY_CTRL_HIB_PULSE |
ALX_PHY_CTRL_HIB_EN;

/* without any activity */
if (!(hw->sleep_ctrl & ALX_SLEEP_ACTIVE)) {
err = alx_write_phy_reg(hw, ALX_MII_IER, 0);
if (err)
return err;
phy |= ALX_PHY_CTRL_IDDQ | ALX_PHY_CTRL_POWER_DOWN;
} else {
if (hw->sleep_ctrl & (ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_CIFS))
mac |= ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_BRD_EN;
if (hw->sleep_ctrl & ALX_SLEEP_CIFS)
mac |= ALX_MAC_CTRL_TX_EN;
if (duplex == DUPLEX_FULL)
mac |= ALX_MAC_CTRL_FULLD;
if (speed == SPEED_1000)
ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED,
ALX_MAC_CTRL_SPEED_1000);
phy |= ALX_PHY_CTRL_DSPRST_OUT;
err = alx_write_phy_ext(hw, ALX_MIIEXT_ANEG,
ALX_MIIEXT_S3DIG10,
ALX_MIIEXT_S3DIG10_SL);
if (err)
return err;
}

alx_enable_osc(hw);
hw->rx_ctrl = mac;
alx_write_mem32(hw, ALX_MASTER, master);
alx_write_mem32(hw, ALX_MAC_CTRL, mac);
alx_write_mem32(hw, ALX_PHY_CTRL, phy);

/* set val of PDLL D3PLLOFF */
val = alx_read_mem32(hw, ALX_PDLL_TRNS1);
val |= ALX_PDLL_TRNS1_D3PLLOFF_EN;
alx_write_mem32(hw, ALX_PDLL_TRNS1, val);

return 0;
}

bool alx_phy_configured(struct alx_hw *hw)
{
u32 cfg, hw_cfg;
Expand Down Expand Up @@ -990,26 +920,6 @@ int alx_clear_phy_intr(struct alx_hw *hw)
return alx_read_phy_reg(hw, ALX_MII_ISR, &isr);
}

int alx_config_wol(struct alx_hw *hw)
{
u32 wol = 0;
int err = 0;

/* turn on magic packet event */
if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
wol |= ALX_WOL0_MAGIC_EN | ALX_WOL0_PME_MAGIC_EN;

/* turn on link up event */
if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY) {
wol |= ALX_WOL0_LINK_EN | ALX_WOL0_PME_LINK;
/* only link up can wake up */
err = alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP);
}
alx_write_mem32(hw, ALX_WOL0, wol);

return err;
}

void alx_disable_rss(struct alx_hw *hw)
{
u32 ctrl = alx_read_mem32(hw, ALX_RXQ0);
Expand Down Expand Up @@ -1121,71 +1031,6 @@ void alx_configure_basic(struct alx_hw *hw)
alx_write_mem32(hw, ALX_WRR, val);
}

int alx_select_powersaving_speed(struct alx_hw *hw, int *speed, u8 *duplex)
{
int i, err;
u16 lpa;

err = alx_read_phy_link(hw);
if (err)
return err;

if (hw->link_speed == SPEED_UNKNOWN) {
*speed = SPEED_UNKNOWN;
*duplex = DUPLEX_UNKNOWN;
return 0;
}

err = alx_read_phy_reg(hw, MII_LPA, &lpa);
if (err)
return err;

if (!(lpa & LPA_LPACK)) {
*speed = hw->link_speed;
return 0;
}

if (lpa & LPA_10FULL) {
*speed = SPEED_10;
*duplex = DUPLEX_FULL;
} else if (lpa & LPA_10HALF) {
*speed = SPEED_10;
*duplex = DUPLEX_HALF;
} else if (lpa & LPA_100FULL) {
*speed = SPEED_100;
*duplex = DUPLEX_FULL;
} else {
*speed = SPEED_100;
*duplex = DUPLEX_HALF;
}

if (*speed == hw->link_speed && *duplex == hw->duplex)
return 0;
err = alx_write_phy_reg(hw, ALX_MII_IER, 0);
if (err)
return err;
err = alx_setup_speed_duplex(hw, alx_speed_to_ethadv(*speed, *duplex) |
ADVERTISED_Autoneg, ALX_FC_ANEG |
ALX_FC_RX | ALX_FC_TX);
if (err)
return err;

/* wait for linkup */
for (i = 0; i < ALX_MAX_SETUP_LNK_CYCLE; i++) {
msleep(100);

err = alx_read_phy_link(hw);
if (err < 0)
return err;
if (hw->link_speed != SPEED_UNKNOWN)
break;
}
if (i == ALX_MAX_SETUP_LNK_CYCLE)
return -ETIMEDOUT;

return 0;
}

bool alx_get_phy_info(struct alx_hw *hw)
{
u16 devs1, devs2;
Expand Down
5 changes: 0 additions & 5 deletions drivers/net/ethernet/atheros/alx/hw.h
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Original file line number Diff line number Diff line change
Expand Up @@ -418,8 +418,6 @@ struct alx_hw {
u8 flowctrl;
u32 adv_cfg;

u32 sleep_ctrl;

spinlock_t mdio_lock;
struct mdio_if_info mdio;
u16 phy_id[2];
Expand Down Expand Up @@ -479,22 +477,19 @@ void alx_reset_pcie(struct alx_hw *hw);
void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
void alx_post_phy_link(struct alx_hw *hw);
int alx_pre_suspend(struct alx_hw *hw, int speed, u8 duplex);
int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
int alx_read_phy_link(struct alx_hw *hw);
int alx_clear_phy_intr(struct alx_hw *hw);
int alx_config_wol(struct alx_hw *hw);
void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
void alx_start_mac(struct alx_hw *hw);
int alx_reset_mac(struct alx_hw *hw);
void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
bool alx_phy_configured(struct alx_hw *hw);
void alx_configure_basic(struct alx_hw *hw);
void alx_disable_rss(struct alx_hw *hw);
int alx_select_powersaving_speed(struct alx_hw *hw, int *speed, u8 *duplex);
bool alx_get_phy_info(struct alx_hw *hw);

static inline u32 alx_speed_to_ethadv(int speed, u8 duplex)
Expand Down
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