Automatic merge of master into stats-before-this-super

src/hotspot/cpu/aarch64/aarch64_sve.ad

@@ -411,21 +411,22 @@ instruct storeV_masked_partial(vReg src, vmemA mem, pRegGov pg, pRegGov pgtmp, r
   ins_pipe(pipe_slow);
 %}
 
-// maskAll
+// maskAll (full or partial predicate size)
 
 instruct vmaskAll_immI(pRegGov dst, immI src) %{
   predicate(UseSVE > 0);
   match(Set dst (MaskAll src));
   ins_cost(SVE_COST);
-  format %{ "sve_ptrue/sve_pfalse $dst\t# mask all (sve) (B/H/S)" %}
+  format %{ "sve_ptrue_lanecnt/sve_pfalse $dst\t# mask all (sve) (B/H/S)" %}
   ins_encode %{
     int con = (int)$src$$constant;
     if (con == 0) {
       __ sve_pfalse(as_PRegister($dst$$reg));
     } else {
       assert(con == -1, "invalid constant value for mask");
       BasicType bt = Matcher::vector_element_basic_type(this);
-      __ sve_ptrue(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt));
+      __ sve_ptrue_lanecnt(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt),
+                           Matcher::vector_length(this));
     }
   %}
   ins_pipe(pipe_slow);
@@ -435,14 +436,22 @@ instruct vmaskAllI(pRegGov dst, iRegIorL2I src, vReg tmp, rFlagsReg cr) %{
   predicate(UseSVE > 0);
   match(Set dst (MaskAll src));
   effect(TEMP tmp, KILL cr);
-  ins_cost(2 * SVE_COST);
+  ins_cost(3 * SVE_COST);
   format %{ "sve_dup $tmp, $src\n\t"
-            "sve_cmpne $dst, $tmp, 0\t# mask all (sve) (B/H/S)" %}
+            "sve_ptrue_lanecnt $dst\n\t"
+            "sve_cmpne $dst, $dst, $tmp, 0\t# mask all (sve) (B/H/S)" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
     Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
+    uint length_in_bytes = Matcher::vector_length_in_bytes(this);
     __ sve_dup(as_FloatRegister($tmp$$reg), size, as_Register($src$$reg));
-    __ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
+    if (length_in_bytes < MaxVectorSize) {
+      __ sve_ptrue_lanecnt(as_PRegister($dst$$reg), size, Matcher::vector_length(this));
+      __ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size,
+                 as_PRegister($dst$$reg), as_FloatRegister($tmp$$reg), 0);
+    } else {
+      __ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
+    }
   %}
   ins_pipe(pipe_slow);
 %}
@@ -451,15 +460,16 @@ instruct vmaskAll_immL(pRegGov dst, immL src) %{
   predicate(UseSVE > 0);
   match(Set dst (MaskAll src));
   ins_cost(SVE_COST);
-  format %{ "sve_ptrue/sve_pfalse $dst\t# mask all (sve) (D)" %}
+  format %{ "sve_ptrue_lanecnt/sve_pfalse $dst\t# mask all (sve) (D)" %}
   ins_encode %{
     long con = (long)$src$$constant;
     if (con == 0) {
       __ sve_pfalse(as_PRegister($dst$$reg));
     } else {
       assert(con == -1, "invalid constant value for mask");
       BasicType bt = Matcher::vector_element_basic_type(this);
-      __ sve_ptrue(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt));
+      __ sve_ptrue_lanecnt(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt),
+                           Matcher::vector_length(this));
     }
   %}
   ins_pipe(pipe_slow);
@@ -469,14 +479,22 @@ instruct vmaskAllL(pRegGov dst, iRegL src, vReg tmp, rFlagsReg cr) %{
   predicate(UseSVE > 0);
   match(Set dst (MaskAll src));
   effect(TEMP tmp, KILL cr);
-  ins_cost(2 * SVE_COST);
+  ins_cost(3 * SVE_COST);
   format %{ "sve_dup $tmp, $src\n\t"
-            "sve_cmpne $dst, $tmp, 0\t# mask all (sve) (D)" %}
+            "sve_ptrue_lanecnt $dst\n\t"
+            "sve_cmpne $dst, $dst, $tmp, 0\t# mask all (sve) (D)" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
     Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
+    uint length_in_bytes = Matcher::vector_length_in_bytes(this);
     __ sve_dup(as_FloatRegister($tmp$$reg), size, as_Register($src$$reg));
-    __ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
+    if (length_in_bytes < MaxVectorSize) {
+      __ sve_ptrue_lanecnt(as_PRegister($dst$$reg), size, Matcher::vector_length(this));
+      __ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size,
+                 as_PRegister($dst$$reg), as_FloatRegister($tmp$$reg), 0);
+    } else {
+      __ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
+    }
   %}
   ins_pipe(pipe_slow);
 %}
@@ -3084,6 +3102,7 @@ instruct reduce_maxF_masked(vRegF dst, vRegF src1, vReg src2, pRegGov pg) %{
             n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
   match(Set dst (MaxReductionV (Binary src1 src2) pg));
   ins_cost(SVE_COST);
+  effect(TEMP_DEF dst);
   format %{ "sve_reduce_maxF $dst, $src1, $pg, $src2\t# maxF reduction predicated (sve)" %}
   ins_encode %{
     __ sve_fmaxv(as_FloatRegister($dst$$reg), __ S, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));
@@ -3098,6 +3117,7 @@ instruct reduce_maxD_masked(vRegD dst, vRegD src1, vReg src2, pRegGov pg) %{
             n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
   match(Set dst (MaxReductionV (Binary src1 src2) pg));
   ins_cost(SVE_COST);
+  effect(TEMP_DEF dst);
   format %{ "sve_reduce_maxD $dst, $src1, $pg, $src2\t# maxD reduction predicated (sve)" %}
   ins_encode %{
     __ sve_fmaxv(as_FloatRegister($dst$$reg), __ D, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));
@@ -3380,6 +3400,7 @@ instruct reduce_minF_masked(vRegF dst, vRegF src1, vReg src2, pRegGov pg) %{
             n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
   match(Set dst (MinReductionV (Binary src1 src2) pg));
   ins_cost(SVE_COST);
+  effect(TEMP_DEF dst);
   format %{ "sve_reduce_minF $dst, $src1, $pg, $src2\t# minF reduction predicated (sve)" %}
   ins_encode %{
     __ sve_fminv(as_FloatRegister($dst$$reg), __ S, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));
@@ -3394,6 +3415,7 @@ instruct reduce_minD_masked(vRegD dst, vRegD src1, vReg src2, pRegGov pg) %{
             n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
   match(Set dst (MinReductionV (Binary src1 src2) pg));
   ins_cost(SVE_COST);
+  effect(TEMP_DEF dst);
   format %{ "sve_reduce_minD $dst, $src1, $pg, $src2\t# minD reduction predicated (sve)" %}
   ins_encode %{
     __ sve_fminv(as_FloatRegister($dst$$reg), __ D, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));

src/hotspot/cpu/aarch64/aarch64_sve_ad.m4

@@ -356,15 +356,16 @@ instruct vmaskAll_imm$1(pRegGov dst, imm$1 src) %{
   predicate(UseSVE > 0);
   match(Set dst (MaskAll src));
   ins_cost(SVE_COST);
-  format %{ "sve_ptrue/sve_pfalse $dst\t# mask all (sve) ($2)" %}
+  format %{ "sve_ptrue_lanecnt/sve_pfalse $dst\t# mask all (sve) ($2)" %}
   ins_encode %{
     ifelse($1, `I', int, long) con = (ifelse($1, `I', int, long))$src$$constant;
     if (con == 0) {
       __ sve_pfalse(as_PRegister($dst$$reg));
     } else {
       assert(con == -1, "invalid constant value for mask");
       BasicType bt = Matcher::vector_element_basic_type(this);
-      __ sve_ptrue(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt));
+      __ sve_ptrue_lanecnt(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt),
+                           Matcher::vector_length(this));
     }
   %}
   ins_pipe(pipe_slow);
@@ -377,19 +378,27 @@ instruct vmaskAll$1(pRegGov dst, ifelse($1, `I', iRegIorL2I, iRegL) src, vReg tm
   predicate(UseSVE > 0);
   match(Set dst (MaskAll src));
   effect(TEMP tmp, KILL cr);
-  ins_cost(2 * SVE_COST);
+  ins_cost(3 * SVE_COST);
   format %{ "sve_dup $tmp, $src\n\t"
-            "sve_cmpne $dst, $tmp, 0\t# mask all (sve) ($2)" %}
+            "sve_ptrue_lanecnt $dst\n\t"
+            "sve_cmpne $dst, $dst, $tmp, 0\t# mask all (sve) ($2)" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
     Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
+    uint length_in_bytes = Matcher::vector_length_in_bytes(this);
     __ sve_dup(as_FloatRegister($tmp$$reg), size, as_Register($src$$reg));
-    __ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
+    if (length_in_bytes < MaxVectorSize) {
+      __ sve_ptrue_lanecnt(as_PRegister($dst$$reg), size, Matcher::vector_length(this));
+      __ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size,
+                 as_PRegister($dst$$reg), as_FloatRegister($tmp$$reg), 0);
+    } else {
+      __ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
+    }
   %}
   ins_pipe(pipe_slow);
 %}')dnl
 dnl
-// maskAll
+// maskAll (full or partial predicate size)
 MASKALL_IMM(I, B/H/S)
 MASKALL(I, B/H/S)
 MASKALL_IMM(L, D)
@@ -1807,6 +1816,7 @@ instruct reduce_$1$2_masked($5 dst, $5 src1, vReg src2, pRegGov pg) %{
             n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
   match(Set dst (translit($1, `m', `M')ReductionV (Binary src1 src2) pg));
   ins_cost(SVE_COST);
+  effect(TEMP_DEF dst);
   format %{ "sve_reduce_$1$2 $dst, $src1, $pg, $src2\t# $1$2 reduction predicated (sve)" %}
   ins_encode %{
     __ sve_f$1v(as_FloatRegister($dst$$reg), __ $4, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

@@ -1232,3 +1232,39 @@ void C2_MacroAssembler::sve_reduce_integral(int opc, Register dst, BasicType bt,
     }
   }
 }
+
+// Set elements of the dst predicate to true if the element number is
+// in the range of [0, lane_cnt), or to false otherwise.
+void C2_MacroAssembler::sve_ptrue_lanecnt(PRegister dst, SIMD_RegVariant size, int lane_cnt) {
+  assert(size != Q, "invalid size");
+  switch(lane_cnt) {
+    case 1: /* VL1 */
+    case 2: /* VL2 */
+    case 3: /* VL3 */
+    case 4: /* VL4 */
+    case 5: /* VL5 */
+    case 6: /* VL6 */
+    case 7: /* VL7 */
+    case 8: /* VL8 */
+      sve_ptrue(dst, size, lane_cnt);
+      break;
+    case 16:
+      sve_ptrue(dst, size, /* VL16 */ 0b01001);
+      break;
+    case 32:
+      sve_ptrue(dst, size, /* VL32 */ 0b01010);
+      break;
+    case 64:
+      sve_ptrue(dst, size, /* VL64 */ 0b01011);
+      break;
+    case 128:
+      sve_ptrue(dst, size, /* VL128 */ 0b01100);
+      break;
+    case 256:
+      sve_ptrue(dst, size, /* VL256 */ 0b01101);
+      break;
+    default:
+      assert(false, "unsupported");
+      ShouldNotReachHere();
+  }
+}

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

@@ -88,6 +88,10 @@
   void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
                            FloatRegister src2, PRegister pg, FloatRegister tmp);
 
+  // Set elements of the dst predicate to true if the element number is
+  // in the range of [0, lane_cnt), or to false otherwise.
+  void sve_ptrue_lanecnt(PRegister dst, SIMD_RegVariant size, int lane_cnt);
+
   // Generate predicate through whilelo, by comparing ZR with an unsigned
   // immediate. rscratch1 will be clobbered.
   inline void sve_whilelo_zr_imm(PRegister pd, SIMD_RegVariant size, uint imm) {

src/hotspot/cpu/aarch64/spin_wait_aarch64.hpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Amazon.com Inc. or its affiliates. All rights reserved.
+ * Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it

src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp

@@ -1820,8 +1820,8 @@ void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2,
         __ teq(xhi, yhi);
         __ teq(xlo, ylo, eq);
       } else {
-        __ subs(xlo, xlo, ylo);
-        __ sbcs(xhi, xhi, yhi);
+        __ subs(Rtemp, xlo, ylo);
+        __ sbcs(Rtemp, xhi, yhi);
       }
     } else {
       ShouldNotReachHere();

src/hotspot/share/c1/c1_LIRGenerator.cpp

@@ -963,6 +963,14 @@ void LIRGenerator::move_to_phi(PhiResolver* resolver, Value cur_val, Value sux_v
   Phi* phi = sux_val->as_Phi();
   // cur_val can be null without phi being null in conjunction with inlining
   if (phi != NULL && cur_val != NULL && cur_val != phi && !phi->is_illegal()) {
+    if (phi->is_local()) {
+      for (int i = 0; i < phi->operand_count(); i++) {
+        Value op = phi->operand_at(i);
+        if (op != NULL && op->type()->is_illegal()) {
+          bailout("illegal phi operand");
+        }
+      }
+    }
     Phi* cur_phi = cur_val->as_Phi();
     if (cur_phi != NULL && cur_phi->is_illegal()) {
       // Phi and local would need to get invalidated

src/hotspot/share/gc/g1/g1OldGenAllocationTracker.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Amazon.com, Inc. or its affiliates. All rights reserved.
+ * Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it

src/hotspot/share/gc/g1/g1OldGenAllocationTracker.hpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Amazon.com, Inc. or its affiliates. All rights reserved.
+ * Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it

src/hotspot/share/runtime/vmThread.hpp

@@ -53,8 +53,7 @@ class VMOperationTimeoutTask : public PeriodicTask {
 };
 
 //
-// A single VMThread (the primordial thread) spawns all other threads
-// and is itself used by other threads to offload heavy vm operations
+// A single VMThread is used by other threads to offload heavy vm operations
 // like scavenge, garbage_collect etc.
 //
 
@@ -78,7 +77,6 @@ class VMThread: public NamedThread {
   void inner_execute(VM_Operation* op);
   void wait_for_operation();
 
- public:
   // Constructor
   VMThread();
 
@@ -87,14 +85,15 @@ class VMThread: public NamedThread {
     guarantee(false, "VMThread deletion must fix the race with VM termination");
   }
 
+  // The ever running loop for the VMThread
+  void loop();
+
+ public:
   bool is_running() const { return Atomic::load(&_is_running); }
 
   // Tester
   bool is_VM_thread() const                      { return true; }
 
-  // The ever running loop for the VMThread
-  void loop();
-
   // Called to stop the VM thread
   static void wait_for_vm_thread_exit();
   static bool should_terminate()                  { return _should_terminate; }

src/java.base/share/classes/sun/security/ssl/ClientHello.java

@@ -568,15 +568,15 @@ public byte[] produce(ConnectionContext context) throws IOException {
                             "No new session is allowed and " +
                             "no existing session can be resumed");
                 }
-
-                if (chc.maximumActiveProtocol.useTLS13PlusSpec() &&
-                        SSLConfiguration.useCompatibilityMode) {
-                    // In compatibility mode, the TLS 1.3 legacy_session_id
-                    // field MUST be non-empty, so a client not offering a
-                    // pre-TLS 1.3 session MUST generate a new 32-byte value.
-                    sessionId =
+            }
+            if (sessionId.length() == 0 &&
+                    chc.maximumActiveProtocol.useTLS13PlusSpec() &&
+                    SSLConfiguration.useCompatibilityMode) {
+                // In compatibility mode, the TLS 1.3 legacy_session_id
+                // field MUST be non-empty, so a client not offering a
+                // pre-TLS 1.3 session MUST generate a new 32-byte value.
+                sessionId =
                         new SessionId(true, chc.sslContext.getSecureRandom());
-                }
             }
 
             ProtocolVersion minimumVersion = ProtocolVersion.NONE;

src/java.base/share/classes/sun/security/ssl/SSLConfiguration.java

@@ -97,7 +97,7 @@ final class SSLConfiguration implements Cloneable {
     static final boolean allowLegacyMasterSecret =
         Utilities.getBooleanProperty("jdk.tls.allowLegacyMasterSecret", true);
 
-    // Allow full handshake without Extended Master Secret extension.
+    // Use TLS1.3 middlebox compatibility mode.
     static final boolean useCompatibilityMode = Utilities.getBooleanProperty(
             "jdk.tls.client.useCompatibilityMode", true);
 

src/java.base/share/man/java.1

@@ -1541,6 +1541,31 @@ and its committed regions.
 .RE
 .RE
 .TP
+.B \f[CB]\-XX:+NeverActAsServerClassMachine\f[R]
+Enable the "Client VM emulation" mode which only uses the C1 JIT
+compiler, a 32Mb CodeCache and the Serial GC.
+The maximum amount of memory that the JVM may use (controlled by the
+\f[CB]\-XX:MaxRAM=n\f[R] flag) is set to 1GB by default.
+The string "emulated\-client" is added to the JVM version string.
+.RS
+.PP
+By default the flag is set to \f[CB]true\f[R] only on Windows in 32\-bit
+mode and \f[CB]false\f[R] in all other cases.
+.PP
+The "Client VM emulation" mode will not be enabled if any of the
+following flags are used on the command line:
+.IP
+.nf
+\f[CB]
+\-XX:{+|\-}TieredCompilation
+\-XX:CompilationMode=mode
+\-XX:TieredStopAtLevel=n
+\-XX:{+|\-}EnableJVMCI
+\-XX:{+|\-}UseJVMCICompiler
+\f[R]
+.fi
+.RE
+.TP
 .B \f[CB]\-XX:ObjectAlignmentInBytes=\f[R]\f[I]alignment\f[R]
 Sets the memory alignment of Java objects (in bytes).
 By default, the value is set to 8 bytes.