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Automatic merge of master into lambda-leftovers
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duke committed Dec 24, 2020
2 parents 55f367b + 57217b5 commit d65c6bc
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Showing 275 changed files with 5,500 additions and 2,264 deletions.
9 changes: 9 additions & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.hpp
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Expand Up @@ -264,6 +264,7 @@ class Assembler : public AbstractAssembler {
SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1),
SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1),
DIVWU_OPCODE = (31u << OPCODE_SHIFT | 459u << 1),
MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1),
MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1),
MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1),
Expand Down Expand Up @@ -524,10 +525,13 @@ class Assembler : public AbstractAssembler {

// Vector-Scalar (VSX) instruction support.
LXV_OPCODE = (61u << OPCODE_SHIFT | 1u ),
LXVL_OPCODE = (31u << OPCODE_SHIFT | 269u << 1),
STXV_OPCODE = (61u << OPCODE_SHIFT | 5u ),
STXVL_OPCODE = (31u << OPCODE_SHIFT | 397u << 1),
LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
MTVSRDD_OPCODE = (31u << OPCODE_SHIFT | 435u << 1),
MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1),
MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1),
Expand Down Expand Up @@ -1343,6 +1347,8 @@ class Assembler : public AbstractAssembler {
inline void divd_( Register d, Register a, Register b);
inline void divw( Register d, Register a, Register b);
inline void divw_( Register d, Register a, Register b);
inline void divwu( Register d, Register a, Register b);
inline void divwu_( Register d, Register a, Register b);

// Fixed-Point Arithmetic Instructions with Overflow detection
inline void addo( Register d, Register a, Register b);
Expand Down Expand Up @@ -2263,6 +2269,8 @@ class Assembler : public AbstractAssembler {
// Vector-Scalar (VSX) instructions.
inline void lxv( VectorSRegister d, int si16, Register a);
inline void stxv( VectorSRegister d, int si16, Register a);
inline void lxvl( VectorSRegister d, Register a, Register b);
inline void stxvl( VectorSRegister d, Register a, Register b);
inline void lxvd2x( VectorSRegister d, Register a);
inline void lxvd2x( VectorSRegister d, Register a, Register b);
inline void stxvd2x( VectorSRegister d, Register a);
Expand All @@ -2277,6 +2285,7 @@ class Assembler : public AbstractAssembler {
inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void mtvsrd( VectorSRegister d, Register a);
inline void mfvsrd( Register d, VectorSRegister a);
inline void mtvsrdd( VectorSRegister d, Register a, Register b);
inline void mtvsrwz( VectorSRegister d, Register a);
inline void mfvsrwz( Register d, VectorSRegister a);
inline void xxspltw( VectorSRegister d, VectorSRegister b, int ui2);
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5 changes: 5 additions & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.inline.hpp
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Expand Up @@ -127,6 +127,8 @@ inline void Assembler::divd( Register d, Register a, Register b) { emit_int32(
inline void Assembler::divd_( Register d, Register a, Register b) { emit_int32(DIVD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
inline void Assembler::divw( Register d, Register a, Register b) { emit_int32(DIVW_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
inline void Assembler::divw_( Register d, Register a, Register b) { emit_int32(DIVW_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
inline void Assembler::divwu( Register d, Register a, Register b) { emit_int32(DIVWU_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
inline void Assembler::divwu_( Register d, Register a, Register b) { emit_int32(DIVWU_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }

// Fixed-Point Arithmetic Instructions with Overflow detection
inline void Assembler::addo( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
Expand Down Expand Up @@ -792,11 +794,14 @@ inline void Assembler::lvsr( VectorRegister d, Register s1, Register s2) { emit
// Vector-Scalar (VSX) instructions.
inline void Assembler::lxv( VectorSRegister d, int ui16, Register a) { assert(is_aligned(ui16, 16), "displacement must be a multiple of 16"); emit_int32( LXV_OPCODE | vsrt_dq(d) | ra0mem(a) | uimm(ui16, 16)); }
inline void Assembler::stxv( VectorSRegister d, int ui16, Register a) { assert(is_aligned(ui16, 16), "displacement must be a multiple of 16"); emit_int32( STXV_OPCODE | vsrs_dq(d) | ra0mem(a) | uimm(ui16, 16)); }
inline void Assembler::lxvl( VectorSRegister d, Register s1, Register b) { emit_int32( LXVL_OPCODE | vsrt(d) | ra0mem(s1) | rb(b)); }
inline void Assembler::stxvl( VectorSRegister d, Register s1, Register b) { emit_int32( STXVL_OPCODE | vsrt(d) | ra0mem(s1) | rb(b)); }
inline void Assembler::lxvd2x( VectorSRegister d, Register s1) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); }
inline void Assembler::lxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
inline void Assembler::stxvd2x( VectorSRegister d, Register s1) { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra(0) | rb(s1)); }
inline void Assembler::stxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra0mem(s1) | rb(s2)); }
inline void Assembler::mtvsrd( VectorSRegister d, Register a) { emit_int32( MTVSRD_OPCODE | vsrt(d) | ra(a)); }
inline void Assembler::mtvsrdd( VectorSRegister d, Register a, Register b) { emit_int32( MTVSRDD_OPCODE | vsrt(d) | ra(a) | rb(b)); }
inline void Assembler::mfvsrd( Register d, VectorSRegister a) { emit_int32( MFVSRD_OPCODE | vsrs(a) | ra(d)); }
inline void Assembler::mtvsrwz( VectorSRegister d, Register a) { emit_int32( MTVSRWZ_OPCODE | vsrt(d) | ra(a)); }
inline void Assembler::mfvsrwz( Register d, VectorSRegister a) { emit_int32( MFVSRWZ_OPCODE | vsrs(a) | ra(d)); }
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1 change: 0 additions & 1 deletion src/hotspot/cpu/ppc/ppc.ad
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Expand Up @@ -3583,7 +3583,6 @@ encode %{
call->_method_handle_invoke = _method_handle_invoke;
call->_vtable_index = _vtable_index;
call->_method = _method;
call->_bci = _bci;
call->_optimized_virtual = _optimized_virtual;
call->_tf = _tf;
call->_entry_point = _entry_point;
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