VHDL Support for Syntax Highlighting

[Thraetaona]

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For context, VHDL (VHSIC Hardware Description Language) is a hardware-descriptive language ("HDL"), first designed by the U.S. DoD in the 1980s, which has since been standardized by as IEEE-1076; alongside Verilog, it is one of the "two main" HDLs in FPGA and ASIC designs.

Currently, GitHub's syntax highlighter does not seem to properly highlight VHDL's syntax; it seems to treat VHDL, which has a syntax similar to Ada and Pascal, as purely Ada. For instance, notice how this sample VHDL code seems to show red "syntax errors" despite consisting of entirely valid VHDL; this is because of VHDL's custom extensions to the Ada language. Also, many other keywords and C-style block comments /* ... */, which are supported in VHDL and not Ada, are also displayed incorrectly.

Additionally, within ``` code fences, there should be a vhd or vhdl option; right now, the only way to get partial syntax highlighting in code fences for VHDL is by labelling it as ada:

-- ```ada
prescaler : entity work.srl_prescaler
	generic map (100e6, 1)
	port map (clk_in_100mhz, ce_out_1hz);
-- ```

[look]

Thanks for the suggestion. I passed this feedback along to the team.

For your reference, the current syntax highlighting is powered by this TextMate grammar. My teammate verified the bug you note exists there. It could be fixed but that repository hasn't been changed in 7 years. 😅

The other option would be to switch our syntax highlighting to use the tree-sitter grammar.