Add archinfo to rz_analysis_plugin_tricore_cs

rizinorg · May 4, 2023 · 8b4c418 · 8b4c418
1 parent 5fd0ed8
commit 8b4c418
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Showing 2 changed files with 57 additions and 38 deletions.
diff --git a/librz/analysis/p/analysis_tricore_cs.c b/librz/analysis/p/analysis_tricore_cs.c
@@ -762,13 +762,28 @@ static RzAnalysisILConfig *il_config(RzAnalysis *analysis) {
 	return cfg;
 }
 
+static int archinfo(RzAnalysis *a, RzAnalysisInfoType query) {
+	switch (query) {
+	case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE:
+		return 2;
+	case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE:
+		return 4;
+	case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN:
+	case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN:
+	case RZ_ANALYSIS_ARCHINFO_CAN_USE_POINTERS:
+	default:
+		return -1;
+	}
+}
+
 RzAnalysisPlugin rz_analysis_plugin_tricore_cs = {
 	.name = "tricore",
 	.desc = "Capstone TRICORE analysis plugin",
 	.license = "LGPL3",
 	.arch = "tricore",
 	.bits = 32,
 	.get_reg_profile = get_reg_profile,
+	.archinfo = archinfo,
 	.op = rz_analysis_tricore_op,
 	.il_config = il_config,
 };

diff --git a/test/db/analysis/tricore b/test/db/analysis/tricore
@@ -2,39 +2,43 @@ NAME=TriCore lea
 FILE=malloc://512
 CMDS=!rz-asm -a tricore -d d916606c
 EXPECT=<<EOF
-lea a6, [a1]-14944
+lea %d6, [%p0]-0x3a60
 EOF
 RUN
 
 NAME=TriCore sub
 FILE=malloc://512
 CMDS=!rz-asm -a tricore -d 200a
 EXPECT=<<EOF
-sub.a sp, 10
+sub.a %sp, 0xa
 EOF
 RUN
 
 NAME=TriCore multi
 FILE=malloc://512
 CMDS=!rz-asm -a tricore -d 0f0200007cb10880f8130200
 EXPECT=<<EOF
-sh d0, d2, d0
-jnz.a a11, 0x00000006
-ld.bu d0, [a15]8
-st.a [sp]76, a15
-mov d0, d0
+
+mov %d0, %d0
+fret
+
+ld.bu %d0, [%a15]8
+st.a [%sp]0x13, %a15
+mov %d0, %d0
 EOF
 RUN
 
 NAME=TriCore multi
 FILE=malloc://512
 CMDS=!rz-asm -a tricore -d 0f0200007cb10880f8130200
 EXPECT=<<EOF
-sh d0, d2, d0
-jnz.a a11, 0x00000006
-ld.bu d0, [a15]8
-st.a [sp]76, a15
-mov d0, d0
+
+mov %d0, %d0
+fret
+
+ld.bu %d0, [%a15]8
+st.a [%sp]0x13, %a15
+mov %d0, %d0
 EOF
 RUN
 
@@ -124,36 +128,36 @@ s 0x80000004
 pd 30
 EOF
 EXPECT=<<EOF
-            0x80000004      8c80           ld.h  d15, [a8]0            ; load half word
+            0x80000004      8c80           ld.h  %d15, [%d8]0          ; load half word
             0x80000006      0000           nop                         ; nop operation
-            0x80000008      8c80           ld.h  d15, [a8]0            ; load half word
+            0x80000008      8c80           ld.h  %d15, [%d8]0          ; load half word
             0x8000000a      0000           nop                         ; nop operation
-            0x8000000c      8c80           ld.h  d15, [a8]0            ; load half word
+            0x8000000c      8c80           ld.h  %d15, [%d8]0          ; load half word
             0x8000000e      0000           nop                         ; nop operation
-            0x80000010      8c80           ld.h  d15, [a8]0            ; load half word
+            0x80000010      8c80           ld.h  %d15, [%d8]0          ; load half word
             0x80000012      0000           nop                         ; nop operation
-            0x80000014      85f12000       ld.w  d1, 0xf0000020        ; load word
-            0x80000018      6f010400       jz.t  d1, 0, 0x80000020     ; jump if zero bit
-            0x8000001c      5d006800       jl    0x800000ec            ; jump and link
-            0x80000020      910000ad       movh.a sp, 53248            ; move high to address
-            0x80000024      d9aa6000       lea   sp, [sp]1056 <0xd0000420> ; load effective address
-            0x80000028      7b00000d       movh  d0, 53248             ; move high
-            0x8000002c      1b008200       addi  d0, d0, 2080          ; add immediate
-            0x80000030      cd80e20f       mtcr  #0xfe28, d0           ; move to core register
-            0x80000034      0d00c004       isync                       ; synchronize instructions
-            0x80000038      7b000008       movh  d0, 32768             ; move high
-            0x8000003c      1b003000       addi  d0, d0, 768           ; add immediate
-            0x80000040      cd40e20f       mtcr  #0xfe24, d0           ; move to core register
-            0x80000044      0d00c004       isync                       ; synchronize instructions
-            0x80000048      4d40e00f       mfcr  d0, #0xfe04           ; move from core register
-            0x8000004c      8ff04701       or    d0, d0, 127           ; bitwise or
-            0x80000050      8f00c801       andn  d0, d0, 128
-            0x80000054      cd40e00f       mtcr  #0xfe04, d0           ; move to core register
-            0x80000058      0d00c004       isync                       ; synchronize instructions
-            0x8000005c      4d40e00f       mfcr  d0, #0xfe04           ; move from core register
-            0x80000060      8f005001       or    d0, d0, 256           ; bitwise or
-            0x80000064      cd40e00f       mtcr  #0xfe04, d0           ; move to core register
-            0x80000068      0d00c004       isync                       ; synchronize instructions
+            0x80000014      85f12000       ld.w  %d1, 0xf0000020       ; load word
+        ,=< 0x80000018      6f010400       jz.t  %e0, 0, -0x7fffffe0   ; jump if zero bit
+       ,==< 0x8000001c      5d006800       jl    -0x7fffff14           ; jump and link
+       ||   0x80000020      910000ad       movh.a %d10, 0xd000         ; move high to address
+       ||   0x80000024      d9aa6000       lea   %d10, [%p10]0x420     ; load effective address
+       ||   0x80000028      7b00000d       movh  %d0, 0xd000           ; move high
+       ||   0x8000002c      1b008200       addi  %d0, 0x820,           ; add immediate
+       ||   0x80000030      cd80e20f       
+       ||   0x80000031      80e2           mov.d %d2, %d14             ; move address to data register
+       ||   0x80000033      0f0d00c0       
+       ||   0x80000034      0d00c004       isync                       ; synchronize instructions
+       ||   0x80000038      7b000008       movh  %d0, 0x8000           ; move high
+       ||   0x8000003c      1b003000       addi  %d0, 0x300,           ; add immediate
+       ||   0x80000040      cd40e20f       
+       ||   0x80000041      40e20f0d       
+       ||   0x80000042      e20f           mul   %d15, %d0             ; multiply signed
+       ||   0x80000044      0d00c004       isync                       ; synchronize instructions
+       ||   0x80000048      4d40e00f       mfcr  %d0, %d0              ; move from core register
+       ||   0x8000004c      8ff04701       
+       ||   0x8000004d      f047018f       
+       ||   0x8000004e      47018f00       and.and.t %d0, %d1, 0xf, %d0, 1
+       ||   0x80000052      c801           ld.a  %e0, [%a15]0          ; load word to address register
 EOF
 RUN