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un.s|utrunc.s|umul.aa.*
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@imbillow
imbillow committed Nov 28, 2024
1 parent 92ca4d1 commit c5b7690
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27 changes: 26 additions & 1 deletion librz/arch/isa/xtensa/xtensa_il.c
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ static const char *eps_tbl[] = {

#define ABS(X) ITE(SGT(X, S32(0)), X, NEG(X))
#define V32(X) UNSIGNED(32, (X))
#define V64(X) UNSIGNED(64, (X))

typedef RzAnalysisLiftedILOp (*fn_analyze_op_il)(XtensaContext *ctx);
typedef RzILOpPure *(fn_op2)(RzILOpBool *x, RzILOpBool *y);
Expand Down Expand Up @@ -1306,6 +1307,25 @@ static RzAnalysisLiftedILOp op_ult_s(XtensaContext *ctx) {
return SETG(REGN(0), FLT(FLOATV32(IREG(1)), FLOATV32(IREG(2))));
}

static RzAnalysisLiftedILOp op_umul_aa(XtensaContext *ctx) {
ut8 half = RRR_half(ctx);
return SEQ3(
SETG("m1", half & 0x1 ? HI16(IREG(0)) : LO16(IREG(0))),
SETG("m2", half & 0x2 ? HI16(IREG(1)) : LO16(IREG(1))),
ACC_set(MUL(V64(VARG("m1")), V64(VARG("m2")))));
}

// FIXME: statusflags
static RzAnalysisLiftedILOp op_un_s(XtensaContext *ctx) {
return SETG(REGN(0), OR(IS_FNAN(FLOATV32(IREG(1))), IS_FNAN(FLOATV32(IREG(2)))));
}

// FIXME: statusflags
static RzAnalysisLiftedILOp op_utrunc_s(XtensaContext *ctx) {
return SETG(REGN(0),
F2INT(32, RZ_FLOAT_RMODE_RNA, FMUL(RZ_FLOAT_RMODE_RNA, FLOATV32(IREG(1)), F32(pow(2, IMM(2))))));
}

#include <rz_il/rz_il_opbuilder_end.h>

static const fn_analyze_op_il fn_tbl[] = {
Expand Down Expand Up @@ -1591,7 +1611,12 @@ static const fn_analyze_op_il fn_tbl[] = {
[XTENSA_INS_UFLOAT_S] = op_ufloat_s,
[XTENSA_INS_ULE_S] = op_ule_s,
[XTENSA_INS_ULT_S] = op_ult_s,

[XTENSA_INS_UMUL_AA_HH] = op_umul_aa,
[XTENSA_INS_UMUL_AA_HL] = op_umul_aa,
[XTENSA_INS_UMUL_AA_LH] = op_umul_aa,
[XTENSA_INS_UMUL_AA_LL] = op_umul_aa,
[XTENSA_INS_UN_S] = op_un_s,
[XTENSA_INS_UTRUNC_S] = op_utrunc_s,
};

void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {
Expand Down
6 changes: 6 additions & 0 deletions test/db/asm/xtensa
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Original file line number Diff line number Diff line change
Expand Up @@ -281,3 +281,9 @@ d "ueq.s b2, f3, f1" 10233b 0x0 (set b2 (! (|| (|| (is_nan (float 0 (var f3) ))
d "float.s f2, a3, 1" 1023ca 0x0 (set f2 (cast 64 false (fbits (fcast_float ieee754-bin32 rna (div (var a3) (bv 32 0x0))))))
d "ule.s b2, f3, f1" 10237b 0x0 (set b2 (&& (! (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) )))) (! (<. (float 0 (var f1) ) (float 0 (var f3) )))))
d "ult.s b2, f3, f1" 10235b 0x0 (set b2 (&& (! (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) )))) (<. (float 0 (var f3) ) (float 0 (var f1) ))))
d "umul.aa.ll a2, a1" 140270 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))))
d "umul.aa.hl a2, a1" 140271 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))))
d "umul.aa.lh a2, a1" 140272 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))))
d "umul.aa.hh a2, a1" 140273 0x0 (seq (set m1 (& (>> (var a2) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (* (cast 64 false (var m1)) (cast 64 false (var m2)))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (& (>> (var acc) (bv 32 0x20) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))))
d "utrunc.s a2, f3, 1" 1023ea 0x0 (set a2 (fcast_int 32 rna (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) ))))
d "un.s b2, f3, f1" 10231b 0x0 (set b2 (|| (is_nan (float 0 (var f3) )) (is_nan (float 0 (var f1) ))))

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