atsamd21: initial implementation usign TC4/5

[maximeborges]

Initial implementation of a monotonic timer using half-period counting with TC4/TC5.

Tested on a custom device using an ATSAMD21G16B.

[Sympatron]

Does this implementation run the timer at 48MHz? If so, why not prescale it to 1MHz? 1µs resolution is plenty for almost any use case and it will generate less overflows and allows for greater intervals to be usable.

[maximeborges]

Does this implementation run the timer at 48MHz? If so, why not prescale it to 1MHz? 1µs resolution is plenty for almost any use case and it will generate less overflows and allows for greater intervals to be usable.

As a first step for simplicity, since there are currently no RTIC v2 monotonic implementation for the SAMD family (now the RTC implementation seems to be ready to use also).
I would definitely accept PR to add support for other chips in the family to improve this one. I'm a bit constrained by time until the end of the month to polish things myself here, but could help other initiatives.