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Fixing processing order of EP0 (control) transactions #41

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4 changes: 4 additions & 0 deletions src/control_pipe.rs
Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,10 @@ impl<B: UsbBus> ControlPipe<'_, B> {
},
};

// Now that we have properly parsed the setup packet, ensure the end-point is no longer in
// a stalled state.
self.ep_out.unstall();

/*sprintln!("SETUP {:?} {:?} {:?} req:{} val:{} idx:{} len:{} {:?}",
req.direction, req.request_type, req.recipient,
req.request, req.value, req.index, req.length,
Expand Down
30 changes: 17 additions & 13 deletions src/device.rs
Original file line number Diff line number Diff line change
Expand Up @@ -169,6 +169,23 @@ impl<B: UsbBus> UsbDevice<'_, B> {

// Pending events for endpoint 0?
if (eps & 1) != 0 {
// Handle EP0-IN conditions first. When both EP0-IN and EP0-OUT have completed,
// it is possible that EP0-OUT is a zero-sized out packet to complete the STATUS
// phase of the control transfer. We have to process EP0-IN first to update our
// internal state properly.
if (ep_in_complete & 1) != 0 {
let completed = self.control.handle_in_complete();

if !B::QUIRK_SET_ADDRESS_BEFORE_STATUS {
if completed && self.pending_address != 0 {
self.bus.set_device_address(self.pending_address);
self.pending_address = 0;

self.device_state = UsbDeviceState::Addressed;
}
}
}

let req = if (ep_setup & 1) != 0 {
self.control.handle_setup()
} else if (ep_out & 1) != 0 {
Expand All @@ -185,19 +202,6 @@ impl<B: UsbBus> UsbDevice<'_, B> {
_ => (),
};

if (ep_in_complete & 1) != 0 {
let completed = self.control.handle_in_complete();

if !B::QUIRK_SET_ADDRESS_BEFORE_STATUS {
if completed && self.pending_address != 0 {
self.bus.set_device_address(self.pending_address);
self.pending_address = 0;

self.device_state = UsbDeviceState::Addressed;
}
}
}

eps &= !1;
}

Expand Down