Update HPFAR_EL2 and ID_AA64DFR0_EL1 fields

Signed-off-by: Sangwan Kwon <[email protected]>
rust-embedded · Oct 25, 2024 · 9107714 · 9107714
1 parent 39369e6
commit 9107714
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Showing 2 changed files with 46 additions and 6 deletions.
diff --git a/src/registers/hpfar_el2.rs b/src/registers/hpfar_el2.rs
@@ -17,7 +17,7 @@ register_bitfields! {u64,
         NS   OFFSET(63) NUMBITS(1) [],
 
         /// Faulting Intermediate Physical Address.
-        FIPA OFFSET(4) NUMBITS(40) []
+        FIPA OFFSET(4) NUMBITS(48) []
     ]
 }
 

diff --git a/src/registers/id_aa64dfr0_el1.rs b/src/registers/id_aa64dfr0_el1.rs
@@ -14,16 +14,56 @@ use tock_registers::{interfaces::Readable, register_bitfields};
 register_bitfields! {u64,
     pub ID_AA64DFR0_EL1 [
         /// Branch Record Buffer Extension.
-        BRBE OFFSET(52) NUMBITS(4) [],
+        ///
+        /// - 0000 Branch Record Buffer Extension not implemented.
+        /// - 0001 Branch Record Buffer Extension implemented.
+        /// - 0010 As 0b0001, and adds support for branch recording at EL3.
+        ///
+        /// All other values are reserved.
+        BRBE OFFSET(52) NUMBITS(4) [
+            NotImplemented = 0b0000,
+            Implemented = 0b0001,
+            Implemented_El3Support = 0b0010,
+        ],
 
         /// Multi-threaded PMU extension.
-        MTPMU OFFSET(48) NUMBITS(4) [],
+        ///
+        /// - 0000 FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, it is IMPLEMENTATION
+        ///        DEFINED whether PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are read/write or RES0.
+        /// - 0001 FEAT_MTPMU and FEAT_PMUv3 implemented. PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT
+        ///        are read/write. When FEAT_MTPMU is disabled, the Effective values of
+        ///        PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are 0.
+        /// - 1111 FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, PMEVTYPER<n>_EL0.MT
+        ///        and PMEVTYPER<n>.MT are RES0.
+        ///
+        /// All other values are reserved.
+        MTPMU OFFSET(48) NUMBITS(4) [
+            NotImplemented = 0b0000,
+            Implemented = 0b0001,
+            NotImplemented_Res0 = 0b1111,
+        ],
 
         /// Trace Buffer Extension.
-        TraceBuffer OFFSET(44) NUMBITS(4) [],
+        ///
+        /// - 0000 Trace Buffer Extension not implemented.
+        /// - 0001 Trace Buffer Extension implemented.
+        /// - 0010 As 0b0001, and adds:
+        ///   - If EL2 and FEAT_FGT are implemented, a fine-grained trap on the TSB CSYNC instruction.
+        ///   - If EL2 is implemented, an EL2 control to override TRBLIMITR_EL1.nVM.
+        ///   - The TRBE Profiling exception extension, FEAT_TRBE_EXC.
+        ///
+        /// All other values are reserved.
+        TraceBuffer OFFSET(44) NUMBITS(4) [
+            NotImplemented = 0b0000,
+            Implemented = 0b0001,
+            Implemented_Trbe = 0b0010,
+        ],
 
         /// Armv8.4 Self-hosted Trace Extension version.
-        TraceFilt OFFSET(40) NUMBITS(4) [],
+        TraceFilt OFFSET(40) NUMBITS(4) [
+            NotImplemented = 0b0000,
+            Implemented = 0b0001,
+        ],
 
         /// Statistical Profiling Extension version.
         PMSVer OFFSET(32) NUMBITS(4) [],
@@ -45,7 +85,7 @@ register_bitfields! {u64,
         TraceVer OFFSET(4) NUMBITS(4) [],
 
         /// Debug architecture version. Indicates presence of Armv8 debug architecture.
-        DebugVer OFFSET(4) NUMBITS(4) [],
+        DebugVer OFFSET(0) NUMBITS(4) [],
     ]
 }