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Fix bitmask vector bit order #380
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@RalfJung looks good? |
I honestly can't tell, I don't really understand the code in this library. We'll see if this makes the Miri tests pass -- once it propagates into the rustc repository. I also have no idea what should happen for cases like |
Yeah, I'm not sure what makes the most sense either. Fwiw size 12 simply doesn't work yet, something is wrong with the intrinsic. When I fix the intrinsic I expect the last element to be the one needing fixing, because LLVM simply specifies the vector element ordering to be dependent on endianness (not just bitmasks, also concatenating vectors into a single integer). An alternative implementation could reverse the vector rather than the bitmask, if that makes it any clearer. |
I'm fine with whatever as long as it is consistent between simd_bitmask and simd_select_bitmask, and documented properly. :) Miri anyway only supports powers of 2 currently. |
We should explain why this is the correct behavior before we commit it, which means expanding our written spec for |
Perhaps we should expose the intrinsics in something like core::intrinsics::simd and use that documentation as the actual semantics |
Any estimate when this will be propagated to the rustc repo? :) |
I just opened rust-lang/rust#121269 |
enable from_bitmask_vector test on little-endian targets Blocked on rust-lang/portable-simd#380 propagating to the rustc repo
…Jung enable from_bitmask_vector test on little-endian targets Blocked on rust-lang/portable-simd#380 propagating to the rustc repo
Fixes #379