Fix MXCSR configuration dependent timing #111139
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Some data-independent timing vector instructions may have subtle data-dependent timing due to MXCSR configuration; dependent on (potentially secret) data instruction retirement may be delayed by one cycle.
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Rollup of 8 pull requests Successful merges: - rust-lang#109677 (Stabilize raw-dylib, link_ordinal, import_name_type and -Cdlltool) - rust-lang#110780 (rustdoc-search: add slices and arrays to index) - rust-lang#110830 (Add FreeBSD cpuset support to `std::thread::available_concurrency`) - rust-lang#111139 (Fix MXCSR configuration dependent timing) - rust-lang#111239 (Remove unnecessary attribute from a diagnostic) - rust-lang#111246 (forbid escaping bound vars in combine) - rust-lang#111251 (Issue 109502 follow up, remove unnecessary Vec::new() from compile_test()) - rust-lang#111261 (Mark `ErrorGuaranteed` constructor as deprecated so people don't use it) Failed merges: r? `@ghost` `@rustbot` modify labels: rollup
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Dependent on the (potentially secret) data some vector instructions operate on, and the content in MXCSR, instruction retirement may be delayed by one cycle. This is a potential side channel.
This PR fixes this vulnerability for the
x86_64-fortanix-unknown-sgxplatform by loading MXCSR with0x1fbfthrough anxrstorinstruction when the enclave is entered and executing anlfenceimmediately after. Other changes of the MXCSR happen only when the enclave is about to be exited and no vector instructions will be executed before it will actually do so. Users of EDP who change the MXCSR and do wish to defend against this side channel, will need to implement the software mitigation described here.cc: @jethrogb @monokles