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Increasing the SIMD size improves the vectorization possibilities #116018

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merged 3 commits into from
Oct 6, 2023
Merged

Increasing the SIMD size improves the vectorization possibilities #116018

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d30f210
Increasing the SIMD size improves the vectorization possibilities
DianQK Sep 21, 2023
910674f
Only check for successful vectorization on wider_reduce_into_iter
DianQK Sep 24, 2023
e300847
Add a wishlist FIXME
scottmcm Oct 6, 2023
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24 changes: 11 additions & 13 deletions tests/codegen/simd/simd-wide-sum.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -11,24 +11,24 @@
#![feature(portable_simd)]

use std::simd::{Simd, SimdUint};
const N: usize = 8;
const N: usize = 16;

#[no_mangle]
// CHECK-LABEL: @wider_reduce_simd
pub fn wider_reduce_simd(x: Simd<u8, N>) -> u16 {
// CHECK: zext <8 x i8>
// CHECK-SAME: to <8 x i16>
// CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
// CHECK: zext <16 x i8>
// CHECK-SAME: to <16 x i16>
// CHECK: call i16 @llvm.vector.reduce.add.v16i16(<16 x i16>
let x: Simd<u16, N> = x.cast();
x.reduce_sum()
}

#[no_mangle]
// CHECK-LABEL: @wider_reduce_loop
pub fn wider_reduce_loop(x: Simd<u8, N>) -> u16 {
// CHECK: zext <8 x i8>
// CHECK-SAME: to <8 x i16>
// CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
// CHECK: zext <16 x i8>
// CHECK-SAME: to <16 x i16>
// CHECK: call i16 @llvm.vector.reduce.add.v16i16(<16 x i16>
let mut sum = 0_u16;
for i in 0..N {
sum += u16::from(x[i]);
Expand All @@ -39,9 +39,9 @@ pub fn wider_reduce_loop(x: Simd<u8, N>) -> u16 {
#[no_mangle]
// CHECK-LABEL: @wider_reduce_iter
pub fn wider_reduce_iter(x: Simd<u8, N>) -> u16 {
// CHECK: zext <8 x i8>
// CHECK-SAME: to <8 x i16>
// CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
// CHECK: zext <16 x i8>
// CHECK-SAME: to <16 x i16>
// CHECK: call i16 @llvm.vector.reduce.add.v16i16(<16 x i16>
x.as_array().iter().copied().map(u16::from).sum()
}

Expand All @@ -52,8 +52,6 @@ pub fn wider_reduce_iter(x: Simd<u8, N>) -> u16 {
#[no_mangle]
// CHECK-LABEL: @wider_reduce_into_iter
pub fn wider_reduce_into_iter(x: Simd<u8, N>) -> u16 {
// CHECK: zext <8 x i8>
// CHECK-SAME: to <8 x i16>
// CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
// CHECK: call i16 @llvm.vector.reduce.add
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x.to_array().into_iter().map(u16::from).sum()
}
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