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Add more context to router idea #10

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@sethp sethp commented May 11, 2024

Leaving this in draft for now, since I wanted to add some details from the IGLOO2 application note too.

@sethp sethp changed the title Update riscv-router.md Add comparison table May 11, 2024
Especially of interest is how "wide open" the FPGA accelerator field seems to be.
- "Acceleration" chips: The best way to do FPGA development seems to be on an FPGA.... but, not "directly," instead using the FPGA to coorindate with the RTL simulator. What's _that_ chip selection look like?
- Amazon will rent you an [F1 instance with a single (1) attached FPGA](https://instances.vantage.sh/aws/ec2/f1.2xlarge) for $1.6500/hr on-demand (~$0.6488/hr spot), which is about $1200 a month ($500 for spot). They've got a density problem, it seems, since the largest size is an [`f1.16xlarge`](https://instances.vantage.sh/aws/ec2/f1.16xlarge) which comes with 8 FPGAs and a whopping 976.0 GiB of RAM with 64 vCPUs; that and the dedicated 25 Gigabit networking suggest they're renting you the whole blade at that point. But: in our (very limited) experience with RTL simulation, a fairly complex model with no acceleration takes on the order of ones of CPUs and tens of _Megabytes_ of memory. Meaning, a burst-credit model for way oversubscribing the CPU and nano- or micro-scale memory (0.5 to 1 GB) might get us equivalent performance to the `f1.2xlarge` at literally 1/100th the cost of the `f1.2xlarge`. But, to sell us that, assuming their blade is already otherwise "minimally sized" for an AWS DC, they'd need to slot some 512 or 1024 FPGAs per blade. Maybe in the `f2` class, eh?
- Or, it's possible that _is_ a good deal for running a workload more than a couple hours a month, and I've wildly missed my guesses above. In which case, the FPGA itself makes up a significant proportion of the price, and the kind of hardware that people use to simulate other hardware costs on the order of tens of thousands of dollars. I sure hope not!
- But, uh, "firesim" (which is the FPGA accelerator underneath chipyard?) [supports](https://docs.fires.im/en/stable/FireSim-Basics.html#choose-your-platform-to-get-started) the Xilinx Alveo U250 (or U280, which is [discontinued](https://www.xilinx.com/products/boards-and-kits/alveo/u280.html)), [Xilinx VCU118](url), and the RHS Research Nitefury II. That's a [$10,000 "accelerator card"](https://www.mouser.com/ProductDetail/AMD-Xilinx/A-U250-A64G-PQ-G?qs=unwgFEO1A6vi%2FTDpEsBygA%3D%3D), a [$10,000 evaluation kit](https://www.xilinx.com/products/boards-and-kits/vcu118.html) (although you can back-order the chip itself inside the evaluation board for a [cool $50,000](https://www.digikey.com/en/products/detail/amd/XCVU9P-L2FLGA2104E/7421960), which, uh 😵‍💫). But, [RHS Research](https://rhsresearch.com/pages/about-us) to the rescue! Their Nitefury II is a M.2 form-factor accelerator for $150, which is an awful lot more "in budget", even if it only seems to be available via [Amazon](https://www.amazon.com/dp/B0B9FMBF6C). Also of interest: https://www.crowdsupply.com/rhs-research & https://github.com/RHSResearchLLC/NiteFury-and-LiteFury .
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@sethp sethp May 11, 2024

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Should we make an FPGA accelerator board?

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and/or, an m.2 to USB4 adapter, a la https://www.amazon.com/dp/B09XJWH5P1

I'm not exactly sure what I'm saying here, but a Framework expansion bay that "fits" the RHS Research modules (at least the adorable 2230 one) would be cool, especially since slamming the little guy deep inside the laptop makes these I/O connectors pretty permanently inaccessible

PicoEVB Rev D image with connectors "highlighted"

Attempts to answer the question "who is this for" & "why do they want it?"
@sethp sethp changed the title Add comparison table Add more context to router idea May 13, 2024
Everything but the price looks really promising; and the cost is ≥50% the PHY chip, for which I did almost no research/cost comparison.
@sethp sethp marked this pull request as ready for review May 13, 2024 02:46
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sethp commented May 13, 2024

ok @dougli1sqrd I think this one is ready for your 👀 ; the margins don't look too great, but everything's looking like it pencils on the back of the envelope to me. What do you think?

I have a rough cut at a development plan too that ought to answer the "what is it/what do we want it to do" questions, but I think this one is big enough without throwing that on top at the moment.

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