Fix long delay during ADC initialization #217
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
As explained in issue stm32-rs#206, the code here is doing the calculation completely wrong. This leads to a multi-second startup delay instead of just a few clock cycles. Fix this by using the correct calculation; currently only ADC clock configurations synchronous to the AHB are supported which makes this quite easy: We just need to delay the given number of cycles * the selected ADC clock prescaler (1, 2, or 4). To make this code future proof against an implementation of asynchronous ADC clock configurations, use a `match` statement here which will fail to compile once the `ASYNCHRONOUS` variant is added to the `CkMode` struct - thus forcing the implementor to take another look at this. Fixes: stm32-rs#206
|
(FYI, you manually need to approve the CI run now due to recent changes with GHA) |
|
Thanks! Very much appreciated |
Rahix
added a commit
to Rahix/pavu-mixer
that referenced
this pull request
Aug 16, 2021
This was fixed upstream [1] and with the switch to the git version of stm32f3xx-hal, we no longer face this issue. [1]: stm32-rs/stm32f3xx-hal#217
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
As explained in issue #206, the code here is doing the calculation completely wrong. This leads to a multi-second startup delay instead of just a few clock cycles.
Fix this by using the correct calculation; currently only ADC clock configurations synchronous to the AHB are supported which makes this quite easy: We just need to delay the given number of cycles * the selected ADC clock prescaler (1, 2, or 4).
To make this code future proof against an implementation of asynchronous ADC clock configurations, use a
matchstatement here which will fail to compile once theASYNCHRONOUSvariant is added to theCkModestruct - thus forcing the implementor to take another look at this.Fixes: #206