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Release 1.4.0. (#8)
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@ooterness
ooterness authored Mar 18, 2021
1 parent 623cf98 commit c69e870
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Showing 54 changed files with 559 additions and 176 deletions.
8 changes: 7 additions & 1 deletion doc/CHANGELOG.md
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Expand Up @@ -38,9 +38,15 @@ This log will be updated for each new release, but may not reflect the latest de

* Hotfix for inoperable router_config_axi block.

## v1.4.0

* Added diagnostic status flags to the internal Ethernet port definition.
* Compatibility improvements for SGMII startup handshake.
* Timing improvements for traffic statistic counters.

# Copyright Notice

Copyright 2019, 2020 The Aerospace Corporation
Copyright 2019, 2020, 2021 The Aerospace Corporation

This file is part of SatCat5.

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4 changes: 3 additions & 1 deletion project/vivado_2015.4/generate_sgmii_gtx.tcl
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Expand Up @@ -35,8 +35,10 @@ proc generate_sgmii_gtx {gt_loc {core_name sgmii_gtx0} {include_shared_logic 1}}
# Create the new IP core and set all parameters.
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name $core_name
set ip_obj [get_ips $core_name]
# Must enable Auto_Negotiation setting or the configuration_vector used in port_sgmii_gtx.vhd
# does nothing.
set_property -dict [list\
CONFIG.Auto_Negotiation false\
CONFIG.Auto_Negotiation true\
CONFIG.RefClkRate 125\
CONFIG.Management_Interface false\
CONFIG.MaxDataRate 1G\
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13 changes: 13 additions & 0 deletions project/vivado_2015.4/ipcores/EthPort_rtl.xml
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Expand Up @@ -117,6 +117,19 @@ along with SatCat5. If not, see <https://www.gnu.org/licenses/>.
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:logicalName>rx_status</spirit:logicalName>
<spirit:description>Diagnostic status flags</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>rx_reset</spirit:logicalName>
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1 change: 1 addition & 0 deletions project/vivado_2015.4/ipcores/ipcore_shared.tcl
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Expand Up @@ -173,6 +173,7 @@ proc ipcore_add_ethport { label pname type } {
set_property physical_name ${pname}_rx_write [ipx::add_port_map "rx_write" $intf]
set_property physical_name ${pname}_rx_error [ipx::add_port_map "rx_error" $intf]
set_property physical_name ${pname}_rx_rate [ipx::add_port_map "rx_rate" $intf]
set_property physical_name ${pname}_rx_status [ipx::add_port_map "rx_status" $intf]
set_property physical_name ${pname}_rx_reset [ipx::add_port_map "rx_reset" $intf]
set_property physical_name ${pname}_tx_clk [ipx::add_port_map "tx_clk" $intf]
set_property physical_name ${pname}_tx_data [ipx::add_port_map "tx_data" $intf]
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6 changes: 5 additions & 1 deletion project/vivado_2015.4/ipcores/wrap_port_adapter.vhd
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Expand Up @@ -38,6 +38,7 @@ entity wrap_port_adapter is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status : out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand All @@ -53,7 +54,8 @@ entity wrap_port_adapter is
mac_rx_last : in std_logic;
mac_rx_write : in std_logic;
mac_rx_error : in std_logic;
max_rx_rate : in std_logic_vector(15 downto 0);
mac_rx_rate : in std_logic_vector(15 downto 0);
mac_rx_status : in std_logic_vector(7 downto 0);
mac_rx_reset : in std_logic;
mac_tx_clk : in std_logic;
mac_tx_data : out std_logic_vector(7 downto 0);
Expand All @@ -79,6 +81,7 @@ sw_rx_last <= sw_rxd.last;
sw_rx_write <= sw_rxd.write;
sw_rx_error <= sw_rxd.rxerr;
sw_rx_rate <= sw_rxd.rate;
sw_rx_status <= sw_rxd.status;
sw_rx_reset <= sw_rxd.reset_p;
sw_tx_clk <= sw_txc.clk;
sw_tx_ready <= sw_txc.ready;
Expand All @@ -94,6 +97,7 @@ mac_rxd.last <= mac_rx_last;
mac_rxd.write <= mac_rx_write;
mac_rxd.rxerr <= mac_rx_error;
mac_rxd.rate <= mac_rx_rate;
mac_rxd.status <= mac_rx_status;
mac_rxd.reset_p <= mac_rx_reset;
mac_txc.clk <= mac_tx_clk;
mac_txc.ready <= mac_tx_ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_axi_mailbox.vhd
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Expand Up @@ -43,6 +43,7 @@ entity wrap_port_axi_mailbox is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status : out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -92,6 +93,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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4 changes: 4 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_crosslink.vhd
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Expand Up @@ -42,6 +42,7 @@ entity wrap_port_crosslink is
pa_rx_write : out std_logic;
pa_rx_error : out std_logic;
pa_rx_rate : out std_logic_vector(15 downto 0);
pa_rx_status : out std_logic_vector(7 downto 0);
pa_rx_reset : out std_logic;
pa_tx_clk : out std_logic;
pa_tx_data : in std_logic_vector(7 downto 0);
Expand All @@ -58,6 +59,7 @@ entity wrap_port_crosslink is
pb_rx_write : out std_logic;
pb_rx_error : out std_logic;
pb_rx_rate : out std_logic_vector(15 downto 0);
pb_rx_status : out std_logic_vector(7 downto 0);
pb_rx_reset : out std_logic;
pb_tx_clk : out std_logic;
pb_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -87,6 +89,7 @@ pa_rx_last <= arxd.last;
pa_rx_write <= arxd.write;
pa_rx_error <= arxd.rxerr;
pa_rx_rate <= arxd.rate;
pa_rx_status<= arxd.status;
pa_rx_reset <= arxd.reset_p;
pa_tx_clk <= atxc.clk;
pa_tx_ready <= atxc.ready;
Expand All @@ -102,6 +105,7 @@ pb_rx_last <= brxd.last;
pb_rx_write <= brxd.write;
pb_rx_error <= brxd.rxerr;
pb_rx_rate <= brxd.rate;
pb_rx_status<= brxd.status;
pb_rx_reset <= brxd.reset_p;
pb_tx_clk <= btxc.clk;
pb_tx_ready <= btxc.ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_gmii_internal.vhd
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Expand Up @@ -50,6 +50,7 @@ entity wrap_port_gmii_internal is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -86,6 +87,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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4 changes: 4 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_inline_status.vhd
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Expand Up @@ -48,6 +48,7 @@ entity wrap_port_inline_status is
lcl_rx_write : out std_logic;
lcl_rx_error : out std_logic;
lcl_rx_rate : out std_logic_vector(15 downto 0);
lcl_rx_status : out std_logic_vector(7 downto 0);
lcl_rx_reset : out std_logic;
lcl_tx_clk : out std_logic;
lcl_tx_data : in std_logic_vector(7 downto 0);
Expand All @@ -64,6 +65,7 @@ entity wrap_port_inline_status is
net_rx_write : in std_logic;
net_rx_error : in std_logic;
net_rx_rate : in std_logic_vector(15 downto 0);
net_rx_status : in std_logic_vector(7 downto 0);
net_rx_reset : in std_logic;
net_tx_clk : in std_logic;
net_tx_data : out std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -93,6 +95,7 @@ lcl_rx_last <= lcl_rxd.last;
lcl_rx_write <= lcl_rxd.write;
lcl_rx_error <= lcl_rxd.rxerr;
lcl_rx_rate <= lcl_rxd.rate;
lcl_rx_status <= lcl_rxd.status;
lcl_rx_reset <= lcl_rxd.reset_p;
lcl_tx_clk <= lcl_txc.clk;
lcl_tx_ready <= lcl_txc.ready;
Expand All @@ -108,6 +111,7 @@ net_rxd.last <= net_rx_last;
net_rxd.write <= net_rx_write;
net_rxd.rxerr <= net_rx_error;
net_rxd.rate <= net_rx_rate;
net_rxd.status <= net_rx_status;
net_rxd.reset_p <= net_rx_reset;
net_txc.clk <= net_tx_clk;
net_txc.ready <= net_tx_ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_rgmii.vhd
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Expand Up @@ -53,6 +53,7 @@ entity wrap_port_rgmii is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -83,6 +84,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_rmii.vhd
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Expand Up @@ -53,6 +53,7 @@ entity wrap_port_rmii is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -81,6 +82,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_serial_auto.vhd
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Expand Up @@ -47,6 +47,7 @@ entity wrap_port_serial_auto is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -76,6 +77,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_serial_spi_clkin.vhd
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Expand Up @@ -44,6 +44,7 @@ entity wrap_port_serial_spi_clkin is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -74,6 +75,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_serial_spi_clkout.vhd
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Expand Up @@ -45,6 +45,7 @@ entity wrap_port_serial_spi_clkout is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -75,6 +76,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_serial_uart_2wire.vhd
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Expand Up @@ -45,6 +45,7 @@ entity wrap_port_serial_uart_2wire is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -74,6 +75,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_serial_uart_4wire.vhd
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Expand Up @@ -44,6 +44,7 @@ entity wrap_port_serial_uart_4wire is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -74,6 +75,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_sgmii_gpio.vhd
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Expand Up @@ -52,6 +52,7 @@ entity wrap_port_sgmii_gpio is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -84,6 +85,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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2 changes: 2 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_port_sgmii_gtx.vhd
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Expand Up @@ -44,6 +44,7 @@ entity wrap_port_sgmii_gtx is
sw_rx_write : out std_logic;
sw_rx_error : out std_logic;
sw_rx_rate : out std_logic_vector(15 downto 0);
sw_rx_status: out std_logic_vector(7 downto 0);
sw_rx_reset : out std_logic;
sw_tx_clk : out std_logic;
sw_tx_data : in std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -75,6 +76,7 @@ sw_rx_last <= rx_data.last;
sw_rx_write <= rx_data.write;
sw_rx_error <= rx_data.rxerr;
sw_rx_rate <= rx_data.rate;
sw_rx_status <= rx_data.status;
sw_rx_reset <= rx_data.reset_p;
sw_tx_clk <= tx_ctrl.clk;
sw_tx_ready <= tx_ctrl.ready;
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4 changes: 4 additions & 0 deletions project/vivado_2015.4/ipcores/wrap_router_inline.vhd
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Expand Up @@ -67,6 +67,7 @@ entity wrap_router_inline is
lcl_rx_write : out std_logic;
lcl_rx_error : out std_logic;
lcl_rx_rate : out std_logic_vector(15 downto 0);
lcl_rx_status : out std_logic_vector(7 downto 0);
lcl_rx_reset : out std_logic;
lcl_tx_clk : out std_logic;
lcl_tx_data : in std_logic_vector(7 downto 0);
Expand All @@ -83,6 +84,7 @@ entity wrap_router_inline is
net_rx_write : in std_logic;
net_rx_error : in std_logic;
net_rx_rate : in std_logic_vector(15 downto 0);
net_rx_status : in std_logic_vector(7 downto 0);
net_rx_reset : in std_logic;
net_tx_clk : in std_logic;
net_tx_data : out std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -142,6 +144,7 @@ lcl_rx_last <= lcl_rxd.last;
lcl_rx_write <= lcl_rxd.write;
lcl_rx_error <= lcl_rxd.rxerr;
lcl_rx_rate <= lcl_rxd.rate;
lcl_rx_status <= lcl_rxd.status;
lcl_rx_reset <= lcl_rxd.reset_p;
lcl_tx_clk <= lcl_txc.clk;
lcl_tx_ready <= lcl_txc.ready;
Expand All @@ -157,6 +160,7 @@ net_rxd.last <= net_rx_last;
net_rxd.write <= net_rx_write;
net_rxd.rxerr <= net_rx_error;
net_rxd.rate <= net_rx_rate;
net_rxd.status <= net_rx_status;
net_rxd.reset_p <= net_rx_reset;
net_txc.clk <= net_tx_clk;
net_txc.ready <= net_tx_ready;
Expand Down
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