Support for multiple top level designs

[benbr8]

This creates the possibility to simulate multiple toplevel designs in parallel with simulators which support this. It is implemented for Questa and Icarus.

One use case for this is simulating designs containing Xilinx IP, as outlined in #158.

Let me know what you think, and sorry for generating so much noise recently ;).

[benbr8]

Hi, is this going to be considered, or should I implement a local solution? I'll be switching jobs, and I need to have a solution ready by end of the month.

[themperek]

Hi, is this going to be considered, or should I implement a local solution? I'll be switching jobs, and I need to have a solution ready by end of the month.

I can do but not sure if I like it as it is now.

I would rather see toplevel_module to return just the first element.
One could add toplevel_module_list or something like this to get the list.
Same for toplevel_library.

Have a feeling this will look better.

[benbr8]

Hi, thanks for the feedback. I'm indifferent about the 'how' of the solution. I added your suggested changes :)

[themperek]

Thank you.