Introduce support for RD-V3-Cfg1, RD-V3-Cfg2, RD-V3-R1 and RD-V3-R1-Cfg1 platforms. #720
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
On RD-V3 and subsequent platforms, the per chip address mapping has been updated to 64GB. This change adjusts the MaxAddressBitsPerChip PCD value accordingly to ensure proper address calculations. Signed-off-by: Dhinesh Balu <[email protected]>
Arm's RD-V3-Cfg1 platform is a variant of the RD-V3 platform. Compared with RD-V3 platform it has a reduced core count of 8 Neoverse-V3 CPUs with an interconnect of size 3x3. There is one CPU per cluster in the system, so it has a total of 8 clusters. To prepare for supporting this platform, add the initial set of ACPI tables and reuse existing ACPI tables where applicable to boot an operating system on this platform. Signed-off-by: Dhinesh Balu <[email protected]>
Arm's RD-V3-Cfg1 reference design fixed virtual platform simulates 8 CPUs and 8GB of RAM. Add initial support for this platform by adding the required platform build configuration files. Signed-off-by: Dhinesh Balu <[email protected]>
RD-V3-Cfg1 platform supports two LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). Signed-off-by: Dhinesh Balu <[email protected]>
Enable the ACPI CPPC mechanism for RD-V3-Cfg1, as defined by the ACPI specification. This implementation uses AMU registers, accessible as Fixed-feature Hardware (FFixedHW), to monitor performance. Non-secure SCMI fast channels are used to communicate with LCP to set the desired performance levels. Note that the RD-V3-Cfg1 platform does not support CPPC revision 1 or earlier. Therefore, the _OSC method is updated to inform the OSPM of this limitation. Signed-off-by: Dhinesh Balu <[email protected]>
Extend SMBIOS support for the RD-V3-Cfg1 reference design fixed virtual platform. This platform features a core count of 8 Neoverse-V3 CPUs. Each CPU includes a 64KB L1 Data cache, a 64KB L1 Instruction cache, and a 2MB L2 cache. Additionally, the platform has an 8MB system-level cache and 8GB of RAM. Signed-off-by: Dhinesh Balu <[email protected]>
On RD-V3 and subsequent platforms, the base address of the second DRAM region is allowed to be located at a platform-defined address range. Therefore, the method of calculating the base address of the second DRAM region based on predefined address bits has been removed. To ensure a modular and uniform implementation across all platforms, this change introduces Platform Configuration Database (PCD) entries to define these base addresses. Signed-off-by: Dhinesh Balu <[email protected]>
Arm's RD-V3-Cfg2 platform is a quad chip configuration of the RD-V3 platform. The Fixed Virtual Platform (FVP) implementation of this platform limits the number of CPUs to 4 Neoverse-V3 CPUs per chip. Each chip has one CPU per cluster, resulting in 4 clusters per chip. To prepare for supporting this platform, add the initial set of ACPI tables and reuse existing ACPI tables where applicable to boot an operating system on this platform. Signed-off-by: Dhinesh Balu <[email protected]>
Arm's RD-V3-Cfg2 reference design fixed virtual platform simulates 4 CPUs per chip, with each chip having a local address mapping of 64GB. Add the necessary build configuration files and Product ID lookup changes. Signed-off-by: Dhinesh Balu <[email protected]>
The RD-V3-Cfg2 platform supports two LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). Additionally, the cluster supports LPI2 (Power-down) state. The LPI implementation also supports combined power state for both core and cluster. Signed-off-by: Dhinesh Balu <[email protected]>
Enable the ACPI CPPC mechanism for RD-V3-Cfg2, as defined by the ACPI specification. This implementation uses AMU registers, accessible as Fixed-feature Hardware (FFixedHW), to monitor performance. Non-secure SCMI fast channels are used to communicate with LCP to set the desired performance levels. The RD-V3-Cfg2 platform does not support CPPC revision 1 or earlier, so the _OSC method is updated to inform the OSPM of this limitation. Signed-off-by: Dhinesh Balu <[email protected]>
Extend SMBIOS support for the RD-V3-Cfg2 reference design fixed virtual platform. This is a quad-chip platform with 4 Neoverse-V3 CPUs per chip. Each CPU includes a 64KB L1 Data cache, a 64KB L1 Instruction cache, and a 2MB L2 cache. The platform also features a 32MB system-level cache and 8GB of RAM. Signed-off-by: Dhinesh Balu <[email protected]>
dhinesh-balu
force-pushed
the
rdv3cfg1_rdv3cfg2_upstream
branch
from
16bc3c1 to
cdbc737
Compare
The Generic Timer base address is changing for platforms being introduced beyond RD-V3 and variants. To maintain uniformity and facilitate reuse of the existing GTDT ACPI table across multiple supported platforms, this change refactors and introduces PCD entries for defining Generic Timer parameters. Key Changes: 1. Added/Modified PCDs to define Generic Timer parameters. 2. Updated GTDT ACPI table logic to reference these PCDs. 3. Ensured backward compatibility with existing platforms. Signed-off-by: Dhinesh Balu <[email protected]>
This change introduces the IoVirtBlkCountPerChip PCD entry used to track the number of I/O virtualization blocks per chip. Signed-off-by: Dhinesh Balu <[email protected]>
This change introduces the SgiMemoryMap4.dsc.inc file which contains the necessary configurations for memory mapping specific to fourth generation platforms. Signed-off-by: Dhinesh Balu <[email protected]>
Arm's RD-V3-R1 platform is a dual chip platform featuring 70 Neoverse-V3 CPUs per chip. The fixed virtual platform (FVP) implementation of this platform limits the number of CPUs to 14 Neoverse-V3 CPUs per chip. To prepare for supporting this platform, add the initial set of ACPI tables and reuse existing ACPI tables where applicable to boot an operating system on this platform. Signed-off-by: Dhinesh Balu <[email protected]>
Arm's RD-V3-R1 platform is a dual chip platform featuring 70 Neoverse-V3 CPUs per chip. The fixed virtual platform (FVP) implementation of this platform limits the number of CPUs to 14 Neoverse-V3 CPUS per chip, with each chip having a local address mapping of 64GB. Add the necessary build configuration files and Product ID lookup changes. Signed-off-by: Dhinesh Balu <[email protected]>
RD-V3-R1 platform supports two LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). Signed-off-by: Dhinesh Balu <[email protected]>
Enable the ACPI CPPC mechanism for RD-V3-R1, as defined by the ACPI specification. This implementation uses AMU registers, accessible as Fixed-feature Hardware (FFixedHW), to monitor performance. Non-secure SCMI fast channels are used to communicate with LCP to set the desired performance levels. The RD-V3-R1 platform does not support CPPC revision 1 or earlier, so the _OSC method is updated to inform the OSPM of this limitation. Signed-off-by: Dhinesh Balu <[email protected]>
Extend SMBIOS support for the RD-V3-R1 reference design fixed vritual platform. This is a dual-chip platform with 14 Poseidon CPUs per chip. Each CPU includes a 64KB L1 Data cache, a 64KB L1 Instruction cache, and a 2MB L2 cache. The platform also features a 70MB system-level cache and 8GB of RAM. Signed-off-by: Dhinesh Balu <[email protected]>
Arm's RD-V3-R1-Cfg1 platform is quad chip variant of the RD-V3-R1 platform. The Fixed Virtual Platform (FVP) implementation of this platform simulates 8 Neoverse-V3 CPUs per chip. Each chip has one CPU per cluster, resulting in 8 clusters per chip. To prepare for supporting this platform, add the initial set of ACPI tables and reuse existing ACPI tables where applicable to boot an operating system on this platform. Signed-off-by: Dhinesh Balu <[email protected]>
Arm's RD-V3-R1-Cfg1 platform is a quad chip configuration of the RD-V3-R1 platform. The fixed virtual platform (FVP) implementation of this platform simulates 8 Neoverse-V3 CPUs per chip, with each chip having a local address mapping of 64GB. Add the necessary build configuration files and Product ID lookup changes. Signed-off-by: Dhinesh Kumar Balu <[email protected]>
RD-V3-R1-CFG1 platform supports two LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). Signed-off-by: Dhinesh Balu <[email protected]>
Enable the ACPI CPPC mechanism for RD-V3-R1-CFG1, as defined by the ACPI specification. This implementation uses AMU registers, accessible as Fixed-feature Hardware (FFixedHW), to monitor performance. Non-secure SCMI fast channels are used to communicate with LCP to set the desired performance levels. The RD-V3-R1-CFG1 platform does not support CPPC revision 1 or earlier, so the _OSC method is updated to inform the OSPM of this limitation. Signed-off-by: Dhinesh Balu <[email protected]>
Extend SMBIOS support for the RD-V3-R1-Cfg1 reference design fixed virtual platform. This is a quad-chip platform with 8 Neoverse-V3 CPUs per chip. Each CPU includes a 64KB L1 Data cache, a 64KB L1 Instruction cache, and a 2MB L2 cache. Additionally, the platform has an 8MB system-level cache and 8GB of RAM. Signed-off-by: Dhinesh Balu <[email protected]>
dhinesh-balu
changed the title
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This patch series adds support for the following reference design platforms,
The changes include implementing necessary ACPI tables, initial configurations,
power management features, and extending SMBIOS support for the platforms along
with a few refactoring changes ensuring backward compatibility.
Compared to the RD-V3 FVP platform RD-V3-Cfg1 FVP has a reduced core count of
8 Neoverse-V3 CPUs, while RD-V3-Cfg2 FVP platform is a quad chip configuration
of the RD-V3 FVP platform with a core count 4 Neoverse-V3 CPUs per chip.
The RD-V3-R1 FVP platform is a dual chip platform with a reduced core count of
14 Neoverse-V3 CPUs per chip, whereas the RD-V3-R1-Cfg1 FVP platform is quad chip
variant that simulates 8 Neoverse-V3 CPUs per chip.