Add Rust and Zig bindings for RH850.

bindings/const_generator.py

@@ -149,6 +149,7 @@
             'm68k.h': 'm68k',
             'ppc.h': 'ppc',
             'riscv.h': 'riscv',
+            'rh850.h': 'rh850',
             's390x.h' : 's390x',
             'tricore.h' : 'tricore',
             'unicorn.h': 'unicorn',

bindings/rust/src/rh850.rs

@@ -0,0 +1,119 @@
+#![allow(non_camel_case_types)]
+
+// RH850 registers
+#[repr(C)]
+#[derive(PartialEq, Debug, Clone, Copy)]
+pub enum RegisterRH850 {
+    INVALID = -1,
+
+    // General purpose registers
+    R0 = 0,
+    R1 = 1,
+    R2 = 2,
+    R3 = 3,
+    R4 = 4,
+    R5 = 5,
+    R6 = 6,
+    R7 = 7,
+    R8 = 8,
+    R9 = 9,
+    R10 = 10,
+    R11 = 11,
+    R12 = 12,
+    R13 = 13,
+    R14 = 14,
+    R15 = 15,
+    R16 = 16,
+    R17 = 17,
+    R18 = 18,
+    R19 = 19,
+    R20 = 20,
+    R21 = 21,
+    R22 = 22,
+    R23 = 23,
+    R24 = 24,
+    R25 = 25,
+    R26 = 26,
+    R27 = 27,
+    R28 = 28,
+    R29 = 29,
+    R30 = 30,
+    R31 = 31,
+
+    // System registers
+    EIPC = 32,
+    EIPSW = 33,
+    FEPC = 34,
+    FEPSW = 35,
+    ECR = 36,
+    PSW = 37,
+    FPSR = 38,
+    FPEPC = 39,
+    FPST = 40,
+    FPCC = 41,
+    FPCFG = 42,
+    FPEC = 43,
+    EIIC = 45,
+    FEIC = 46,
+    CTPC = 48,
+    CTPSW = 49,
+    CTBP = 52,
+    EIWR = 60,
+    FEWR = 61,
+    BSEL = 63,
+
+    // system registers, selection ID 1
+    MCFG0 = 64,
+    RBASE = 65,
+    EBASE = 66,
+    INTBP = 67,
+    MCTL = 68,
+    PID = 69,
+    SCCFG = 75,
+    SCBP = 76,
+
+    // system registers, selection ID 2
+    HTCFG0 = 96,
+    MEA = 102,
+    ASID = 103,
+    MEI = 104,
+    PC = 288,
+
+    ENDING = 289,
+}
+
+impl RegisterRH850 {
+    // Alias registers
+    // (assoc) ZERO = 0,
+    // (assoc) SP = 3,
+    // (assoc) EP = 30,
+    // (assoc) LP = 31,
+    pub const ZERO: RegisterRH850 = RegisterRH850::R0;
+    pub const SP: RegisterRH850 = RegisterRH850::R3;
+    pub const EP: RegisterRH850 = RegisterRH850::R30;
+    pub const LP: RegisterRH850 = RegisterRH850::R31;
+}
+
+impl From<RegisterRH850> for i32 {
+    fn from(r: RegisterRH850) -> Self {
+        r as i32
+    }
+}
+
+#[repr(i32)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+pub enum RH850CpuModel {
+    UC_CPU_RH850_ANY = 0,
+}
+
+impl From<RH850CpuModel> for i32 {
+    fn from(value: Riscv32CpuModel) -> Self {
+        value as i32
+    }
+}
+
+impl From<&RH850CpuModel> for i32 {
+    fn from(value: &RH850CpuModel) -> Self {
+        (*value) as i32
+    }
+}

bindings/zig/unicorn/rh850_const.zig

@@ -0,0 +1,95 @@
+// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+pub const rh850Const = enum(c_int) {
+	RH850_SYSREG_SELID0 = 32,
+	RH850_SYSREG_SELID1 = 64,
+	RH850_SYSREG_SELID2 = 96,
+	RH850_SYSREG_SELID3 = 128,
+	RH850_SYSREG_SELID4 = 160,
+	RH850_SYSREG_SELID5 = 192,
+	RH850_SYSREG_SELID6 = 224,
+	RH850_SYSREG_SELID7 = 256,
+
+// RH850 global purpose registers
+
+	RH850_REG_R0 = 0,
+	RH850_REG_R1 = 1,
+	RH850_REG_R2 = 2,
+	RH850_REG_R3 = 3,
+	RH850_REG_R4 = 4,
+	RH850_REG_R5 = 5,
+	RH850_REG_R6 = 6,
+	RH850_REG_R7 = 7,
+	RH850_REG_R8 = 8,
+	RH850_REG_R9 = 9,
+	RH850_REG_R10 = 10,
+	RH850_REG_R11 = 11,
+	RH850_REG_R12 = 12,
+	RH850_REG_R13 = 13,
+	RH850_REG_R14 = 14,
+	RH850_REG_R15 = 15,
+	RH850_REG_R16 = 16,
+	RH850_REG_R17 = 17,
+	RH850_REG_R18 = 18,
+	RH850_REG_R19 = 19,
+	RH850_REG_R20 = 20,
+	RH850_REG_R21 = 21,
+	RH850_REG_R22 = 22,
+	RH850_REG_R23 = 23,
+	RH850_REG_R24 = 24,
+	RH850_REG_R25 = 25,
+	RH850_REG_R26 = 26,
+	RH850_REG_R27 = 27,
+	RH850_REG_R28 = 28,
+	RH850_REG_R29 = 29,
+	RH850_REG_R30 = 30,
+	RH850_REG_R31 = 31,
+
+// RH850 system registers, selection ID 0
+	RH850_REG_EIPC = 32,
+	RH850_REG_EIPSW = 33,
+	RH850_REG_FEPC = 34,
+	RH850_REG_FEPSW = 35,
+	RH850_REG_ECR = 36,
+	RH850_REG_PSW = 37,
+	RH850_REG_FPSR = 38,
+	RH850_REG_FPEPC = 39,
+	RH850_REG_FPST = 40,
+	RH850_REG_FPCC = 41,
+	RH850_REG_FPCFG = 42,
+	RH850_REG_FPEC = 43,
+	RH850_REG_EIIC = 45,
+	RH850_REG_FEIC = 46,
+	RH850_REG_CTPC = 48,
+	RH850_REG_CTPSW = 49,
+	RH850_REG_CTBP = 52,
+	RH850_REG_EIWR = 60,
+	RH850_REG_FEWR = 61,
+	RH850_REG_BSEL = 63,
+
+// RH850 system regusters, selection ID 1
+	RH850_REG_MCFG0 = 64,
+	RH850_REG_RBASE = 65,
+	RH850_REG_EBASE = 66,
+	RH850_REG_INTBP = 67,
+	RH850_REG_MCTL = 68,
+	RH850_REG_PID = 69,
+	RH850_REG_SCCFG = 75,
+	RH850_REG_SCBP = 76,
+
+// RH850 system registers, selection ID 2
+	RH850_REG_HTCFG0 = 96,
+	RH850_REG_MEA = 102,
+	RH850_REG_ASID = 103,
+	RH850_REG_MEI = 104,
+	RH850_REG_PC = 288,
+	RH850_REG_ENDING = 289,
+
+// RH8509 Registers aliases.
+
+	RH850_REG_ZERO = 0,
+	RH850_REG_SP = 3,
+	RH850_REG_EP = 30,
+	RH850_REG_LP = 31,
+
+};

bindings/zig/unicorn/unicorn_const.zig

@@ -23,7 +23,8 @@ pub const unicornConst = enum(c_int) {
 	ARCH_RISCV = 8,
 	ARCH_S390X = 9,
 	ARCH_TRICORE = 10,
-	ARCH_MAX = 11,
+	ARCH_RH850 = 11,
+	ARCH_MAX = 12,
 
 	MODE_LITTLE_ENDIAN = 0,
 	MODE_BIG_ENDIAN = 1073741824,
@@ -50,6 +51,7 @@ pub const unicornConst = enum(c_int) {
 	MODE_SPARC32 = 4,
 	MODE_SPARC64 = 8,
 	MODE_V9 = 16,
+	MODE_RH850 = 4,
 	MODE_RISCV32 = 4,
 	MODE_RISCV64 = 8,
 
@@ -75,6 +77,7 @@ pub const unicornConst = enum(c_int) {
 	ERR_HOOK_EXIST = 19,
 	ERR_RESOURCE = 20,
 	ERR_EXCEPTION = 21,
+	ERR_OVERFLOW = 22,
 	MEM_READ = 16,
 	MEM_WRITE = 17,
 	MEM_FETCH = 18,
@@ -140,11 +143,15 @@ pub const unicornConst = enum(c_int) {
 	CTL_TB_FLUSH = 10,
 	CTL_TLB_FLUSH = 11,
 	CTL_TLB_TYPE = 12,
+	CTL_TCG_BUFFER_SIZE = 13,
+	CTL_CONTEXT_MODE = 14,
 
 	PROT_NONE = 0,
 	PROT_READ = 1,
 	PROT_WRITE = 2,
 	PROT_EXEC = 4,
 	PROT_ALL = 7,
+	CTL_CONTEXT_CPU = 1,
+	CTL_CONTEXT_MEMORY = 2,
 
 };