nexys2-verilog-samples

Some verilog examples to run on a Digilent Nexys2.

counter and sevenseg are verilog ports of the vhdl examples found at:

https://github.com/duncanspumpkin/FPGA-Nexys-2-Beginner

Examples:

• counter: Use onboard leds to binary count. Speed is determined by switches.
• sevenseg: Stopwatch which uses btn<0> for on/off.