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[Hardware][CPU] Multi-LoRA implementation for the CPU backend #11100
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c8a8c5b
Added Multi-LoRA implementation for the CPU backend
Akshat-Tripathi 3545ac1
Readded final
Akshat-Tripathi 2b3c650
Decoupled PunicaWrapperCPU from PunicaWrapperGPU
Akshat-Tripathi cc0bd6c
Fixed typing
Akshat-Tripathi dc9091a
Renamed lora op directories
Akshat-Tripathi 410b746
Fixed tests
Akshat-Tripathi 8eab6a6
Merge branch 'main' into multi_lora_cpu
Akshat-Tripathi 5dfcf62
Removed one-to-one correspondence between triton and torch ops
Akshat-Tripathi 651dc04
Fixed mypy error
Akshat-Tripathi d1026bb
Removed redundant optionals
Akshat-Tripathi 2840445
Merge branch 'main' into multi_lora_cpu
mosalov 41c518f
Renamed add_input to add_inputs in punica_cpu.py.
mosalov abb03e5
Merge branch 'main' into multi_lora_cpu
mosalov d212fc9
Optimize kernel test
jeejeelee dcb1794
Merge branch 'main' of https://github.com/vllm-project/vllm into mult…
jeejeelee 3a684b8
Modify test name
jeejeelee c9b9f63
Merge branch 'main' of https://github.com/vllm-project/vllm into mult…
jeejeelee acdb4e3
Merge branch 'main' into multi_lora_cpu
Akshat-Tripathi cfa082f
Removed assert
Akshat-Tripathi 8eaf7ec
Merge branch 'main' into multi_lora_cpu
Akshat-Tripathi bd54243
Merge branch 'main' of https://github.com/vllm-project/vllm into mult…
jeejeelee 21c3799
Resolve test conflicts
jeejeelee aeaf078
Merge branch 'main' of https://github.com/vllm-project/vllm into mult…
jeejeelee 61c42cf
Sync main
jeejeelee 0d19f03
Make isort happy
jeejeelee 5af9cbb
Make yapf happy
jeejeelee 202aca3
run-cpu-test.sh now runs multi-lora tests
Akshat-Tripathi 76444f4
Updated compatibility docs
Akshat-Tripathi 64c700f
Update .buildkite/run-cpu-test.sh
Akshat-Tripathi 06399bc
Lint
Akshat-Tripathi 69eb3dc
Lint2
Akshat-Tripathi e208468
Merge branch 'main' of https://github.com/vllm-project/vllm into mult…
jeejeelee d8cb9af
Reduce test memory
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@DarkLight1337 Are our CPU vendor willing to provide hardware testing for these? Who should we contact?
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I remember there is no numa node restriction for CPU TP, so I think we can just change
VLLM_CPU_OMP_THREADS_BIND=48-92
to something likeVLLM_CPU_OMP_THREADS_BIND=48-70|71-92
to enable TP, even if these cores are on same numa node.There was a problem hiding this comment.
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My bad, I meant to ask if the CPU LoRA testing should be placed here. If so, we might need to contact the CPU vendor?
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@jeejeelee Hi, I think it may be easier to run the offline lora case? Thus we don't need to download the weights file
https://github.com/vllm-project/vllm/blob/main/.buildkite/run-cpu-test.sh#L33
https://github.com/vllm-project/vllm/blob/main/examples/multilora_inference.py
CC @bigPYJ1151
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@zhouyuan Do you mean adding
multilora_inference.py
to https://github.com/vllm-project/vllm/blob/main/.buildkite/run-cpu-test.sh#L33?There was a problem hiding this comment.
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Yes, the target is to enable a test to verify the lora code path on CPU backend