drivers: pinmux stm32F1 remap AFIO without changing the SWJ_CFG #38741

FRASTM · 2021-09-22T12:17:28Z

Change the SPI1_REMAP bit of the AFIO_MAPR of the stm32F1x soc
without changing the SWJ_CFG[2:0]: Serial wire JTAG configuration

fix #38354

Signed-off-by: Francois Ramu [email protected]

drivers/pinmux/pinmux_stm32.c

FRASTM · 2021-09-23T07:19:22Z

OK,
going to change all remap bits of the AFIO_MAPR register,
It takes the same formula as the LL_GPIO_AF_EnableRemap_xxx without changing the AFIO_MAPR_SWJ_CFG bits.
Remapping on the AFIO_MAPR2 is not to change (LL_GPIO_AF_EnableRemap_xxx does not set the AFIO_MAPR_SWJ_CFG bits)

disable clock after AFIO setting

drivers/pinmux/pinmux_stm32.c

ABOSTM · 2021-09-24T12:49:59Z

drivers/pinmux/pinmux_stm32.c

-			/* PB8/PB9 */
-			LL_GPIO_AF_RemapPartial2_CAN1();
+			/* PB8/PB9 (CAN_REMAP = 0b10) */
+			MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP,


Using CMSIS API to modify this register may cause instability:
as per reference manual:

So when modifying the register, it starts by reading the register, with undetermined value for SWJ_CFG,
this undetermined value is then written back to the register. Leading to undetermined behavior of SWJ

This is for me the reason why LL API, manipulates SWJ_CFG sytematically for AFIO_MAPR register and set an invalid SWJ_CFG value to have no effect.
So I think we should keep the original LL API.

For remapping SPI1, we will have:

/* enable remap */ #if defined(CONFIG_GPIO_STM32_SWJ_ENABLE) /* reset state */ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG_RESET)); #elif defined(CONFIG_GPIO_STM32_SWJ_NONJTRST) /* released PB4 */ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG_NOJNTRST)); #elif defined(CONFIG_GPIO_STM32_SWJ_NOJTAG) /* released PB4 PB3 PA15 */ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG_JTAGDISABLE)); #elif defined(CONFIG_GPIO_STM32_SWJ_DISABLE) /* released PB4 PB3 PA13 PA14 PA15 */ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG_DISABLE)); #endif

For disabling remap of SPI1, we will have:

/* disable remap */ #if defined(CONFIG_GPIO_STM32_SWJ_ENABLE) /* reset state */ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG_RESET); #elif defined(CONFIG_GPIO_STM32_SWJ_NONJTRST) /* released PB4 */ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG_NOJNTRST); #elif defined(CONFIG_GPIO_STM32_SWJ_NOJTAG) /* released PB4 PB3 PA15 */ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG_JTAGDISABLE); #elif defined(CONFIG_GPIO_STM32_SWJ_DISABLE) /* released PB4 PB3 PA13 PA14 PA15 */ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG_DISABLE); #endif

FRASTM · 2021-09-24T15:39:22Z

In the stm32F1x, AF remap and debug I/O configuration register (AFIO_MAPR) cannot read the SWJ_CFG bits. The modify register macro must apply the Serial wire JTAG configuration from the CONFIG and not from the MAPR register content.
This new version is redefining enable/disable remap macro depending on the the CONFIG_GPIO_STM32_SWJ_xxx position
and not from the MAPR register.

erwango · 2021-09-24T16:02:43Z

drivers/pinmux/pinmux_stm32.c

+#if defined(CONFIG_GPIO_STM32_SWJ_ENABLE)
+/* reset state */
+#define enable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR,\
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG_RESET))
+#elif defined(CONFIG_GPIO_STM32_SWJ_NONJTRST)
+/* released PB4 */
+#define enable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG_NOJNTRST))
+#elif defined(CONFIG_GPIO_STM32_SWJ_NOJTAG)
+/* released PB4 PB3 PA15 */
+#define enable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG_JTAGDISABLE))
+#elif defined(CONFIG_GPIO_STM32_SWJ_DISABLE)
+/* released PB4 PB3 PA13 PA14 PA15 */
+#define enable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG_DISABLE))
+#endif
+
+/* enable remap : modify MAPR and keep the AFIO_MAPR_SWJ_CFG_x */
+#if defined(CONFIG_GPIO_STM32_SWJ_ENABLE)
+/* reset state */
+#define enable_partial_remap(REMAP_PIN, PARTIAL_REMAP) \
+			MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				(PARTIAL_REMAP | AFIO_MAPR_SWJ_CFG_RESET))
+#elif defined(CONFIG_GPIO_STM32_SWJ_NONJTRST)
+/* released PB4 */
+#define enable_partial_remap(REMAP_PIN, PARTIAL_REMAP) \
+			MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				(PARTIAL_REMAP | AFIO_MAPR_SWJ_CFG_NOJNTRST))
+#elif defined(CONFIG_GPIO_STM32_SWJ_NOJTAG)
+/* released PB4 PB3 PA15 */
+#define enable_partial_remap(REMAP_PIN, PARTIAL_REMAP) \
+			MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				(PARTIAL_REMAP | AFIO_MAPR_SWJ_CFG_JTAGDISABLE))
+#elif defined(CONFIG_GPIO_STM32_SWJ_DISABLE)
+/* released PB4 PB3 PA13 PA14 PA15 */
+#define enable_partial_remap(REMAP_PIN, PARTIAL_REMAP) \
+			MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				(PARTIAL_REMAP | AFIO_MAPR_SWJ_CFG_DISABLE))
+#endif
+
+/* disable remap : modify MAPR and keep the AFIO_MAPR_SWJ_CFG_x */
+#if defined(CONFIG_GPIO_STM32_SWJ_ENABLE)
+/* reset state */
+#define disable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR,\
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				AFIO_MAPR_SWJ_CFG_RESET)
+#elif defined(CONFIG_GPIO_STM32_SWJ_NONJTRST)
+/* released PB4 */
+#define disable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				AFIO_MAPR_SWJ_CFG_NOJNTRST)
+#elif defined(CONFIG_GPIO_STM32_SWJ_NOJTAG)
+/* released PB4 PB3 PA15 */
+#define disable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
+#elif defined(CONFIG_GPIO_STM32_SWJ_DISABLE)
+/* released PB4 PB3 PA13 PA14 PA15 */
+#define disable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR, \
+				(REMAP_PIN | AFIO_MAPR_SWJ_CFG), \
+				AFIO_MAPR_SWJ_CFG_DISABLE)
+#endif


What about something more factorized like:

if defined(CONFIG_GPIO_STM32_SWJ_ENABLE) /* reset state */ #define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_RESET #elif defined(CONFIG_GPIO_STM32_SWJ_NONJTRST) /* released PB4 */ #define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_RESET AFIO_MAPR_SWJ_CFG_NOJNTRST #elif defined(CONFIG_GPIO_STM32_SWJ_NOJTAG) /* released PB4 PB3 PA15 */ #define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_RESET AFIO_MAPR_SWJ_CFG_JTAGDISABLE #elif defined(CONFIG_GPIO_STM32_SWJ_DISABLE) /* released PB4 PB3 PA13 PA14 PA15 */ #define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_RESET AFIO_MAPR_SWJ_CFG_DISABLE #endif #define enable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR,\ (REMAP_PIN | AFIO_MAPR_SWJ_CFG), \ (REMAP_PIN | Z_AFIO_REMAP)) #define enable_partial_remap(REMAP_PIN, PARTIAL_REMAP) \ MODIFY_REG(AFIO->MAPR, \ (REMAP_PIN | AFIO_MAPR_SWJ_CFG), \ (PARTIAL_REMAP | Z_AFIO_REMAP)) #define disable_remap(REMAP_PIN) MODIFY_REG(AFIO->MAPR,\ (REMAP_PIN | AFIO_MAPR_SWJ_CFG), \ Z_AFIO_REMAP)

should Z_AFIO_REMAP be defined based on the CONFIG_GPIO_STM32_SWJ_xxx defnition :

#if defined(CONFIG_GPIO_STM32_SWJ_ENABLE) /* reset state */ #define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_RESET #elif defined(CONFIG_GPIO_STM32_SWJ_NONJTRST) /* released PB4 */ #define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_NOJNTRST #elif defined(CONFIG_GPIO_STM32_SWJ_NOJTAG) /* released PB4 PB3 PA15 */ #define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_JTAGDISABLE #elif defined(CONFIG_GPIO_STM32_SWJ_DISABLE) /* released PB4 PB3 PA13 PA14 PA15 */ #define Z_AFIO_REMAP AFIO_MAPR_SWJ_CFG_DISABLE #endif

FRASTM · 2021-09-27T07:32:06Z

more factorized using Z_AFIO_REMAP

erwango

The remap part looks good

erwango · 2021-09-28T09:38:33Z

drivers/pinmux/pinmux_stm32.c

@@ -383,6 +383,8 @@ int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
 #endif
 	}

+	LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_AFIO);


For now, AFIO clock is not taken into account in gpio clocks.
So disabling it, here will prevent any further GPIO programmation, such as button.
So I agree current situation is not clean, but I'd prefer we limit changes on that part right now (and postpone to V3.0.0)

so, removing the commit

ABOSTM · 2021-09-28T09:55:28Z

drivers/pinmux/pinmux_stm32.c

 		} else {
-			LL_GPIO_AF_DisableRemap_TIM3();
+			enable_partial_remap(AFIO_MAPR_TIM3_REMAP,


should it be disable_remap() ?

this is a partial remap on 2-bit TIM3_REMAP[1:0] (disable_remap is for 1-bit like SPI1_REMAP or I2C1_REMAP)

erwango · 2021-09-28T14:35:45Z

@ck-telecom, can you review, or at least test and see if fixes your issue ?

ck-telecom · 2021-09-29T15:04:28Z

SPI1 remap works well with CONFIG_GPIO_STM32_SWJ_NOJTAG=y

Change the REMAP bits of the AFIO_MAPR of the stm32F1x soc with local MACRO without changing the SWJ_CFG (write-only bits). The serial wire JTAG configuration is taken from the Z_AFIO_REMAP (value of the CONFIG_GPIO_STM32_SWJ_xxx)) and not read from the MAPR register. It accesses to the MAPR register directly instead of LL functions. Note that Remapping on the MAPR2 is not to change. Signed-off-by: Francois Ramu <[email protected]>

github-actions bot added the platform: STM32 ST Micro STM32 label Sep 22, 2021

erwango reviewed Sep 22, 2021

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FRASTM force-pushed the spi1_remap branch from d57a5cb to 254b646 Compare September 23, 2021 06:59

FRASTM mentioned this pull request Sep 23, 2021

stm32: stm32f10x JTAG realated gpio repmap didn't works #38354

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FRASTM force-pushed the spi1_remap branch from 1bb65a7 to d14aba7 Compare September 23, 2021 08:47

FRASTM marked this pull request as ready for review September 23, 2021 08:53

FRASTM requested a review from ABOSTM as a code owner September 23, 2021 08:53

FRASTM force-pushed the spi1_remap branch from d14aba7 to 1e01746 Compare September 23, 2021 08:55

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drivers/pinmux/pinmux_stm32.c Outdated Show resolved Hide resolved

FRASTM force-pushed the spi1_remap branch from 1e01746 to 13c99f7 Compare September 23, 2021 09:04

FRASTM changed the title ~~drivers: pinmux stm32F1 remap spi1 without changing the SWJ_CFG~~ drivers: pinmux stm32F1 remap AFIO without changing the SWJ_CFG Sep 23, 2021

zephyrbot added the area: Pinmux label Sep 23, 2021

zephyrbot requested a review from mnkp September 23, 2021 15:14

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FRASTM force-pushed the spi1_remap branch from 13c99f7 to 304fc19 Compare September 24, 2021 15:42

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FRASTM force-pushed the spi1_remap branch from 304fc19 to 8392097 Compare September 27, 2021 07:31

FRASTM force-pushed the spi1_remap branch from 8392097 to 244aa19 Compare September 27, 2021 07:50

FRASTM mentioned this pull request Sep 28, 2021

stm32f1 gpio AF remap ll function without AFIO_MAPR_SWJ_CFG zephyrproject-rtos/hal_stm32#118

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FRASTM force-pushed the spi1_remap branch from e6ca321 to ac1a56e Compare October 1, 2021 06:58

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erwango added this to the v3.0.0 milestone Oct 4, 2021

erwango requested review from nashif and cfriedt October 4, 2021 12:42

cfriedt merged commit e763061 into zephyrproject-rtos:main Oct 4, 2021

GeorgeCGV mentioned this pull request Mar 7, 2022

Missing SPI SCK on STM32F103vctx #43452

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drivers: pinmux stm32F1 remap AFIO without changing the SWJ_CFG #38741

drivers: pinmux stm32F1 remap AFIO without changing the SWJ_CFG #38741

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drivers: pinmux stm32F1 remap AFIO without changing the SWJ_CFG #38741

drivers: pinmux stm32F1 remap AFIO without changing the SWJ_CFG #38741

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