Merge branch 'master' into newCapModel3

src/processor_sim.py

@@ -1,9 +1,5 @@
 #!/usr/bin/env python
 # -*- coding: utf-8 -*-
-# Disabling then immediately enabling again the invalid-name pylint
-# check allows to skip pylint checking for the module name.
-# pylint: disable=invalid-name
-# pylint: enable=invalid-name
 
 """
 simulates running a program through a processor architecture
@@ -40,8 +36,8 @@
 #
 # author:       Mohammed El-Afifi (ME)
 #
-# environment:  Visual Studio Code 1.95.1, python 3.12.7, Fedora release
-#               40 (Forty)
+# environment:  Visual Studio Code 1.95.2, python 3.13.0, Fedora release
+#               41 (Forty One)
 #
 # notes:        This is a private program.
 #

src/processor_utils/__init__.py

@@ -31,8 +31,8 @@
 #
 # author:       Mohammed El-Afifi (ME)
 #
-# environment:  Visual Studio Code 1.95.1, python 3.12.7, Fedora release
-#               40 (Forty)
+# environment:  Visual Studio Code 1.95.2, python 3.13.0, Fedora release
+#               41 (Forty One)
 #
 # notes:        This is a private program.
 #
@@ -457,7 +457,7 @@ def _get_preds2(
     return _get_preds(processor, unit, unit_map)
 
 
-def _get_proc_units(graph: DiGraph) -> Generator[FuncUnit, None, None]:
+def _get_proc_units(graph: DiGraph) -> Generator[FuncUnit]:
     """Create units for the given processor graph.
 
     `graph` is the processor.
@@ -503,7 +503,7 @@ def _get_roles(
 
 def _get_std_edge(
     edge: Sequence[str], unit_registry: SelfIndexSet[ICaseString]
-) -> Generator[str, None, None]:
+) -> Generator[str]:
     """Return a validated edge.
 
     `edge` is the edge to validate.

src/processor_utils/_checks.py

@@ -32,8 +32,8 @@
 #
 # author:       Mohammed El-Afifi (ME)
 #
-# environment:  Visual Studio Code 1.95.1, python 3.12.7, Fedora release
-#               40 (Forty)
+# environment:  Visual Studio Code 1.95.2, python 3.13.0, Fedora release
+#               41 (Forty One)
 #
 # notes:        This is a private program.
 #
@@ -123,7 +123,7 @@ def chk_non_empty(
 
     """
     if not more_itertools.first_true(
-        in_ports, pred=lambda port: port in processor
+        in_ports, pred=basics.Self(processor)(basics.in_)
     ):
         raise exception.EmptyProcError("No input ports found")
 
@@ -525,14 +525,7 @@ def _do_cap_checks(
     processor: DiGraph,
     cap_checks: Iterable[
         Callable[
-            [
-                DiGraph,
-                Generator[object, None, None],
-                str,
-                list[Any],
-                tuple[Any, ...],
-            ],
-            None,
+            [DiGraph, Generator[object], str, list[Any], tuple[Any, ...]], None
         ]
     ],
 ) -> None:
@@ -559,7 +552,7 @@ def _do_cap_checks(
 
 def _filter_by_cap(
     post_ord: Iterable[_T], capability: object, processor: Graph
-) -> Generator[_T, None, None]:
+) -> Generator[_T]:
     """Filter the given units by the specified capability.
 
     `post_ord` is the post-order of the processor functional units.

src/processor_utils/_port_defs.py

@@ -31,8 +31,8 @@
 #
 # author:       Mohammed El-Afifi (ME)
 #
-# environment:  Visual Studio Code 1.95.1, python 3.12.7, Fedora release
-#               40 (Forty)
+# environment:  Visual Studio Code 1.95.2, python 3.13.0, Fedora release
+#               41 (Forty One)
 #
 # notes:        This is a private program.
 #
@@ -52,7 +52,7 @@
 _T = typing.TypeVar("_T")
 
 
-def get_in_ports(processor: DiGraph) -> Generator[Any, None, None]:
+def get_in_ports(processor: DiGraph) -> Generator[Any]:
     """Find the input ports.
 
     `processor` is the processor to find whose input ports.
@@ -62,7 +62,7 @@ def get_in_ports(processor: DiGraph) -> Generator[Any, None, None]:
     return _get_ports(processor.in_degree)
 
 
-def get_out_ports(processor: DiGraph) -> Generator[Any, None, None]:
+def get_out_ports(processor: DiGraph) -> Generator[Any]:
     """Find the output ports.
 
     `processor` is the processor to find whose output ports.
@@ -98,7 +98,7 @@ def __init__(self, proc_supplier: object) -> None:
     out_ports: Iterable[object]
 
 
-def _get_ports(degrees: Iterable[Iterable[_T]]) -> Generator[_T, None, None]:
+def _get_ports(degrees: Iterable[Iterable[_T]]) -> Generator[_T]:
     """Find the ports with respect to the given degrees.
 
     `degrees` are the degrees of all units.

src/sim_services/_instr_sinks.py

@@ -31,8 +31,8 @@
 #
 # author:       Mohammed El-Afifi (ME)
 #
-# environment:  Visual Studio Code 1.95.1, python 3.12.7, Fedora release
-#               40 (Forty)
+# environment:  Visual Studio Code 1.95.2, python 3.13.0, Fedora release
+#               41 (Forty One)
 #
 # notes:        This is a private program.
 #
@@ -114,7 +114,7 @@ def _get_candidates(
     @staticmethod
     def _get_new_guests(
         src_unit: str, instructions: Iterable[int]
-    ) -> collections.abc.Generator[HostedInstr, None, None]:
+    ) -> collections.abc.Generator[HostedInstr]:
         """Prepare new hosted instructions.
 
         `src_unit` is the old host of instructions.

tests/test_sim.py

@@ -32,7 +32,7 @@
 #
 # author:       Mohammed El-Afifi (ME)
 #
-# environment:  Visual Studio Code 1.95.1, python 3.13.0, Fedora release
+# environment:  Visual Studio Code 1.95.2, python 3.13.0, Fedora release
 #               41 (Forty One)
 #
 # notes:        This is a private program.
@@ -236,8 +236,8 @@ def test_stalled_outputs_are_not_flushed(
             chain([[[], "R1", "ALU"], [["R1"], "R2", "ALU"]], extra_instr_lst),
         )
         cores = starmap(
-            lambda name, width: UnitModel(
-                name, width, {"ALU": False}, LockInfo(True, True)
+            lambda *unit_params: UnitModel(
+                *unit_params, {"ALU": False}, LockInfo(True, True)
             ),
             [("core 1", 1), ("core 2", 1 + len(extra_instr_lst))],
         )