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| <img src="images/proj_icon_a.svg" title="IceChips" align="right" vertical-align="top" width="6.124%"> | ||
| <img src="images/proj_icon_b.svg" title="IceChips" align="right" vertical-align="top" width="3.484%"> | ||
| <img src="images/proj_icon_c.svg" title="IceChips" align="right" vertical-align="top" width="3.453%"> | ||
| <br /> | ||
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| # ice-chips-verilog | ||
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| [![Build Status][ico-travisci]][link-travisci] | ||
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| [topdesc]: #desc | ||
| I'm focusing on the 74xx family: devices that were TTL originally (bipolar technologies such as LS, AS), that are now implemented as CMOS (HC, HCT, LV or many other technology variations) | ||
| The 74LS, 74HC, 74HCT family of chips in Verilog for Electronic Design Automation | ||
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| Fully validated by test bench · Parametrized code · DELAY parameters for timing simulation | ||
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| IceChips is built to support the [Icestudio][link-icestudio] and [FPGAwars][link-fpgawars] manifesto: | ||
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| <Open Hardware driven by Open Source> | ||
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| ## Getting Started | ||
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| The easiest way to use these devices is [download the collection](/releases/latest) and open it in the Icestudio design environment. | ||
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| In Icestudio, go to `Tools > Collections > Add` and select the downloaded .zip file. Place and wire up your components, run and test the result. There's a variety of ways to provide inputs and view outputs; but no need for actual parts, wires or power supply. | ||
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| Alternatively, you can download an individual device (.v file) and use it in your own simulation in Verilog. This is the way to go if you wish to set the parameters for #bits, #inputs per gate, #blocks in a device. See the Index to browse devices. | ||
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| ## Index | ||
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|   [Devices by type and name](device-index.md) | ||
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| #### What are the 7400-series TTL chips? | ||
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|   They are digital logic: Gates, multiplexers, counters, registers, adders, multipliers and more | ||
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|   [7400-series integrated circuits (Wikipedia)][link-wiki-7400] | ||
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| ## Icestudio Design Flow | ||
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| Welcome to virtual breadboarding. | ||
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| #### Index | ||
| > [Devices by type and name](device-index.md) | ||
| Icestudio provides circuit simulation (for digital circuits) that's arbitrarily scalable. Explore, build and create, but most importantly, get near-instant feedback in testing your real hardware design. Each time you add a new input or a gate, hit "Build" and "Upload". In the parlance of a silicon fab, you've gone through a "spin". But you're actually programming a reusable and fairly inexpensive FPGA. | ||
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| #### Who | ||
| > Hobbyist who wants to program an FPGA, or do general digital circuit simulation, and wants to do it from already-proven building blocks | ||
| CAD-style layout using drag and drop | ||
| -> Full Verilog model | ||
| -> Validation of design rules & connectivity | ||
| -> Synthesis of circuit | ||
| -> Bitstream to FPGA | ||
| -> Live circuit to test or put in-situ | ||
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| #### What | ||
| > Basic logic such as gates, registers, multiplexers, counters, adders, but also non-retriggerable monostable multivibrators | ||
| It's done with entirely open source tools (the IceStorm toolchain); and most of the magic is due to the representation in Hardware Description Language, i.e. Verilog, because HDL is translatable to H: | ||
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| #### Why | ||
| > I noticed the [74xx chips][link-wiki7400] do not exist in one place as an open-source catalogue in Verilog (or in VHDL to my knowledge). To see them and create a simulation with them, you would need to open up Xilinx Vivado or ISE or the Intel/Altera Quartus IDE. You can find free [simulators and digital playgrounds][link-websim], but what to type into them? You'll need [IceChips](source-7400). | ||
| - Once you have a system fully modelled in HDL, you have everything. The HDL is used to generate hardware in any way you require, in a process called [logic synthesis][link-wiki-synth] | ||
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| ...Of course you could just buy a breadboard and the ICs. But that's going by different logic. | ||
| - The toolchain can synthesize the circuit onto an expanding selection of FPGAs; see [Icestudio][link-icestudio] for details | ||
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| <img src="images/TTL.png" title="TTL ICs on a real board" width="25%" height="25%"> | ||
| - What's cool about the Icestudio graphical editing, with internal Verilog, is the hierarchy, encapsulation and layering that it makes easy and explicit; this promotes compositional design; it means scalability and testability | ||
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| ## What to Expect | ||
| ## Tests and Validation | ||
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| * Each device validated by test bench | ||
| * Implemented formally: A single Input/Output/Code template; industry pin names; consistent Verilog | ||
| * Fully parametrized (so you could pretend that a quad or a hex buffer/line driver is actually 64 bits for your FPGA design; you could turn a triple 3-input NAND gate - the workhorse [7410](source-7400/7410.v) - into a heptal 5-input NAND gate just by plugging in the two numbers) | ||
| A test bench accompanies every device (74xx-tb.v file with 74xx.v file) and the tests are run automatically. Click on the "tests" badge below the main title at top of page to see the results of the validation run. | ||
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| > Coming soon in 2019: As you see, the sequential devices are being worked on (counters etc.), with tri-state capability being worked on as we speak. | ||
| Tests are a definitive feature of this library. They must be: | ||
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| > Please contact me if you have a request (and the device number is less than about 74699!) | ||
| 1. Comprehensive | ||
| 2. Meaningful (each test adding value) | ||
| 3. Annotated with descriptions | ||
| 4. Pass/Fail when run | ||
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| ## Purpose | ||
| The tests are for documentation and transparency and create a kind of audit trail - that's in addition to their role in correctness! | ||
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| Using one module per logic device (in other words: encapsulated Verilog) promotes compositional design and bottom-up design so that hopefully large logic blocks/cores (from a crypto accelerator, or a [coin mining][link-coinmining] FPGA, to a CPU?) can be created if you validate and spec out each module, step by step. All you need to do is wire the modules together! | ||
| The tests are actively Pass/Fail, because they "assert" and they log a failure message if the stated condition is not met. They are not just doing a demonstration run of the device, with a waveform output. See more details in the Validation Contract and in the project code. | ||
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| > Stay tuned because exciting things will happen once the library is built out more! | ||
| Coverage will continue at the highest standard as the library expands going forward. | ||
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| ## Usage | ||
| [usage]: #usage | ||
| You have to "trust but verify" when scaling up a hardware design from lower-layer components. | ||
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| The test benches can be run using the open-source simulator Icarus Verilog: [Installation][link-iverilogi], [Getting Started][link-iverilogs]. | ||
| #### Validation Contract | ||
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| With it installed on your system you can run a command like the following that specifies the required input files and one output file (.vvp): | ||
| The stamp of approval comes from the test bench code, but more is involved: Scripts and templates generate the code files of IceChips, and also ensure they are validated reliably and completely. | ||
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|   [Validation scheme](docs/validation-scheme.md) · How the the code files and .ice components are validated | ||
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| #### Running the tests on your machine | ||
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| <details> | ||
| <summary>Details</summary> | ||
| <br /> | ||
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| The test benches can be run using the open source simulator Icarus Verilog: [Installation][link-iverilogi], [Getting Started][link-iverilogs]. | ||
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| With it installed, you can run a command like the following that specifies the required input files and one output file (.vvp): | ||
| ``` | ||
| > iverilog -g2012 -o 7400-tb.vvp ../includes/helper.v ../includes/tbhelper.v 7400-tb.v 7400.v | ||
| > iverilog -g2012 -o7400-tb.vvp ../includes/helper.v ../includes/tbhelper.v 7400-tb.v 7400.v | ||
| ``` | ||
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| It then requires a second step: Run the Icarus Verilog simulator/runtime to see the tests run, with results logged to the console: | ||
| ``` | ||
| > vvp 7400-tb.vvp | ||
| ``` | ||
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| If you're interested in looking even closer, the above vvp run stores signal and timing data of all the inputs, outputs, and the connection paths in the .vcd file, so run GTKWave viewer to see it all as a waveform: [Installation][link-gtkwavei], [Getting Started][link-gtkwaves]. | ||
| If you're interested in looking even closer, the above "vvp" run stores all signal and timing data - inputs, outputs, and the connection paths between them - in a .vcd file, so run GTKWave viewer to see the run as a waveform: [Installation][link-gtkwavei], [Getting Started][link-gtkwaves]. | ||
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| With GTKWave installed, just click on the .vcd file to open. | ||
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| <img src="images/GTK.png" title="Simulation waveform" width="50%" height="50%"> | ||
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| </details> | ||
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| ## Technical Notes | ||
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|   [Implementation info, quirks, challenges in the technology, usage notes, and some bibliographic and specialty interest links](docs/technical-notes.md) | ||
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| ## Other Resources for your Digital Project | ||
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| To brush up on digital logic design, or get started with an EDA flow to create, test out and tape-out your project: | ||
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| <details> | ||
| <summary>Topics to get started</summary> | ||
| <br /> | ||
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| - [Combinational Circuit versus Sequential Circuit][link-web-comb-seq] | ||
| - [RTL Description][link-web-rtl] · Register Transfer Level Description | ||
| - [HDLs][link-web-hdls] · Hardware Description Languages | ||
| - [Logic Simulation][link-web-logic-sim] | ||
| - [Logic Synthesis][link-web-logic-synth] | ||
| - [Logic Friday (Program)][link-web-logic-friday] | ||
| - [Espresso Logic Minimizer (Program)][link-web-esp-logic-min] | ||
| - [EDA][link-web-eda] · Electronic Design Automation | ||
| - [FPGAs][link-web-fpgas] · Field-Programmable Gate Arrays | ||
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| </details> | ||
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| Clarification about this design flow versus PCB (Printed Circuit Board) flow: | ||
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| <details> | ||
| <summary>PCB design flow</summary> | ||
| <br /> | ||
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| Simulating and testing your design can put you in a position to populate your components onto a custom PCB (Printed Circuit Board) to be manufactured. | ||
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| You have a head start because you have a digital circuit that you know meets all its specs. | ||
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| However, it's a different workflow area that you'll have to get into for a PCB: A different type of visual editing ("schematic capture"); placing, routing and design of layout for manufacture; verification of design rules - this time for geometric/electrical properties - for manufacture. | ||
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| Note: Having said that, using 74xx standard parts will set you up well for using PCB software, since the parts are well-known and modelled for geometric/electrical properties. | ||
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| The following keywords are related to PCBs and are **not** part of the present workflow: | ||
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| - Ngspice | ||
| - SPICE | ||
| - Eagle | ||
| - Gerber format | ||
| - Most software programs that have CAD in them (KiCAD) and the ones that have PCB in them (LibrePCB) | ||
| - gEDA suite (for the most part) | ||
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| </details> | ||
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| ## This project gains inspiration from | ||
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| [www.homebrewcpuring.org][link-homebrew] · Amazing Homebrew CPUs | ||
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| [Hackaday Homebrew CPU projects][link-hackbrew] · More Homebrew CPUs | ||
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| [FPGAwars list of projects][link-fpgawarsp] developed with Open Source FPGAs, including CPUs | ||
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| ## Acknowledgments | ||
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| Coming soon. | ||
| Juan González-Gómez [@Obijuan], Jesús Arroyo Torrens, Salvador E. Tropea, Democrito · for Icestudio collections | ||
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| Warren Toomey [@DoctorWkt] · for inspiration because he builds real CPUs, and for using early versions of these devices | ||
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| Eddie Hung [@FPGeh] · for Yosys advice and feedback | ||
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| [digitaljs.tilk.eu](http://digitaljs.tilk.eu) Marek Materzok [@tilk] · for helpful feedback and has an amazing convenient simulator "DigitalJS Online" | ||
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| [www.edaboard.com](https://www.edaboard.com/threads/two-dimensional-input-output-ports-in-verilog.208692) "mrflibble" · provided solution for 2-dimensional inputs to a module | ||
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| ["Inside the vintage 74181 ALU chip"](http://www.righto.com/2017/03/inside-vintage-74181-alu-chip-how-it.html) Ken Shirriff · invaluable info on the 74181 and a fabulous simulator in the browser | ||
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| Marcus Lindholm · SVG graphic design help | ||
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| [www.msarnoff.org/chipdb](http://www.msarnoff.org/chipdb/list) Matt Sarnoff · chip and pin info | ||
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| ["TTL_74xx_DIL.m4"](https://fossies.org/linux/pcb/lib/TTL_74xx_DIL.m4) Thomas Nau, "diplib" in PCB for Linux distribution · chip and pin info | ||
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| [www.referencedesigner.com/tutorials](http://www.referencedesigner.com/tutorials/verilog/verilog_01.php) · practical intro to Verilog with examples, tutorials, quizzes | ||
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| [www.doulos.com/knowhow](https://www.doulos.com/knowhow/verilog_designers_guide/sequential_always_blocks) · practical intro to design and concepts in Verilog | ||
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| [www.verilogpro.com](https://www.verilogpro.com/verilog-generate-configurable-rtl) · practical intro to generate loops and elaboration | ||
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| #### And to these supporting pieces of technology: | ||
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| [Icestudio][link-icestudio] and Apio built on top of IceStorm, Yosys, Arachne-pnr | ||
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| [Yosys][link-yosys] synthesis by Clifford Wolf | ||
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| [Icarus Verilog][link-iverilog] simulator by Stephen Williams | ||
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| [GTKWave][link-gtkwavei] for viewing waveforms | ||
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| ## <!-- --> | ||
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| © 2018-2020 Tim Rudy | ||
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| [ico-license]: https://img.shields.io/badge/license-GPL--3.0%2B-blue.svg | ||
| [ico-language]: https://img.shields.io/badge/Verilog-100%25-orange.svg | ||
| [ico-travisci]: images/passed.svg | ||
|
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| [link-travisci]: https://travis-ci.org/TimRudy/ice-chips-verilog | ||
| [link-wiki7400]: https://en.wikipedia.org/wiki/List_of_7400_series_integrated_circuits | ||
| [link-websim]: https://www.google.com/search?q=free+web+verilog+editor+simulator | ||
| [link-travisci]: https://travis-ci.com/TimRudy/ice-chips-verilog "See the latest build and test report" | ||
| [link-icestudio]: https://icestudio.io | ||
| [link-icestudiob]: https://github.com/FPGAwars/icestudio-blocks/wiki | ||
| [link-openfpgat]: https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki | ||
| [link-fpgawars]: https://fpgawars.github.io | ||
| [link-fpgawarsp]: https://fpgawars.github.io/#projects | ||
| [link-wiki-7400]: https://en.wikipedia.org/wiki/List_of_7400_series_integrated_circuits | ||
| [link-wiki-synth]: https://en.wikipedia.org/wiki/Logic_synthesis | ||
| [link-web-comb-seq]: https://www.google.com/search?q=Combinational+versus+Sequential+Circuit | ||
| [link-web-rtl]: https://www.google.com/search?q=RTL+Description | ||
| [link-web-logic-sim]: https://www.google.com/search?q=Logic+Simulation+in+HDL | ||
| [link-web-logic-synth]: https://www.google.com/search?q=Logic+Synthesis | ||
| [link-web-logic-friday]: https://www.google.com/search?q=Logic+Friday | ||
| [link-web-esp-logic-min]: https://www.google.com/search?q=Espresso+Logic+Minimizer | ||
| [link-web-hdls]: https://www.google.com/search?q=Hardware+Description+Languages | ||
| [link-web-eda]: https://www.google.com/search?q=Electronic+Design+Automation | ||
| [link-web-fpgas]: https://www.google.com/search?q=Field-Programmable+Gate+Arrays | ||
| [link-coinmining]: http://whattomine.com | ||
| [link-iverilogi]: http://iverilog.wikia.com/wiki/Installation_Guide | ||
| [link-iverilogs]: http://iverilog.wikia.com/wiki/Getting_Started | ||
| [link-homebrew]: https://www.homebrewcpuring.org/ringhome.html | ||
| [link-hackbrew]: https://hackaday.io/list/25846-homebrew-cpu | ||
| [link-yosys]: http://www.clifford.at/yosys | ||
| [link-iverilog]: http://iverilog.icarus.com | ||
| [link-iverilogi]: https://iverilog.fandom.com/wiki/Installation_Guide | ||
| [link-iverilogs]: https://iverilog.fandom.com/wiki/Getting_Started | ||
| [link-iverilogu]: https://iverilog.fandom.com/wiki/User_Guide | ||
| [link-gtkwavei]: http://gtkwave.sourceforge.net | ||
| [link-gtkwaves]: http://iverilog.wikia.com/wiki/GTKWAVE | ||
| [link-gtkwaves]: https://iverilog.fandom.com/wiki/GTKWAVE |
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