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Fixed errors reported by quartus for successful build #4

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g-radam
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@g-radam g-radam commented Jul 11, 2019

I wanted to use these logic gates within Quartus 18.1 Lite IDE, but found that Quartus had numerous build issues. I modified the for loops to use i=i+1 rather than post-increment (is this valid syntax?) & added genblock labels (which are optional) but were reported as errors in Quartus. Files build fine now.

TimRudy added a commit that referenced this pull request Jan 20, 2020
- Add generate block labels (~/pull/4)
- Fix yosys/Icestudio synthesis error
- Add tests related to asynchronous/synchronous set and clear
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TimRudy commented Feb 2, 2020

  • The block labels are put in
  • I'll test for the "i=i+1" versus "i++" issue when Quartus Prime Lite v19.1 Windows version becomes available, because I'd prefer to stay with the "i++" (https://fpgasoftware.intel.com/?edition=lite)
  • Did you try a higher language level setting, Verilog 2001, SystemVerilog?
    Thanks very much

@TimRudy TimRudy closed this Feb 2, 2020
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