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Add a test for issue 4159 #4161

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Jun 11, 2024
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Add a test for issue 4159 #4161

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9431d9f
Add a test for issue 4159
jackkoenig Jun 11, 2024
992eaf7
Update src/test/scala/chiselTests/ChiselEnum.scala
jackkoenig Jun 11, 2024
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24 changes: 24 additions & 0 deletions src/test/scala/chiselTests/ChiselEnum.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -401,6 +401,30 @@ class ChiselEnumSpec extends ChiselFlatSpec with Utils {
assertTesterPasses(new CastToUIntTester)
}

// This is a bug but fixing it may break user code
// See https://github.com/chipsalliance/chisel/issues/4159
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it should "preserve legacy width behavior" in {
val verilog = ChiselStage.emitSystemVerilog(new RawModule {
val out1, out2, out3 = IO(Output(UInt(8.W)))
val e = EnumExample.e1
val x = e.asUInt
val y = e.asTypeOf(UInt())
val z = e.asTypeOf(UInt(e.getWidth.W))
out1 := Cat(1.U, x)
out2 := Cat(1.U, y)
out3 := Cat(1.U, z)
// The bug is that the width of x is 7 but the value of out1 is 3
x.getWidth should be(7)
x.getWidth should be(EnumExample.getWidth)
y.widthOption should be(None)
z.getWidth should be(7)
})
// The bug is that all of these should be the same as out3, or the widths above are wrong
verilog should include("assign out1 = 8'h3;")
verilog should include("assign out2 = 8'h3;")
verilog should include("assign out3 = 8'h81;")
}
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Scalatest doesn't have XFAIL, right? This would be better as that if it's supported. Alternatively, this could be a should not include which is the correct thing.

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I don't think ScalaTest has an XFAIL per se, more of should not include yeah. Are you suggesting I also add should not for the "correct" output when we fix this (ie. verilog should not include("assign out1 = 8'h81;") and verilog should not include("assign out2 = 8'h81;"))? Or are you suggesting something else?


it should "cast literal UInts to enums correctly" in {
assertTesterPasses(new CastFromLitTester)
}
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