Fix bug in zero-width memory removal

[seldridge]

Correctly remove all extraneous connections to all types of memory
ports (read, write, readwrite) for zero-width memories. Previously,
only read ports were correctly handled.

Contributor Checklist

• [n/a] Did you add Scaladoc to every public function/method?
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• Did you add at least one test demonstrating the PR?
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Type of Improvement

• bug fix

API Impact

None.

Backend Code Generation Impact

None.

Desired Merge Strategy

• Squash: The PR will be squashed and merged (choose this if you have no preference.

Release Notes

None.

Reviewer Checklist (only modified by reviewer)

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[ekiwi]

LGTM 🚢

Good test!

[jackkoenig]

Suggested change

	private def makeZero(tpe: ir.Type): ir.Type = tpe match {
	case ClockType => UIntType(IntWidth(0))
	case a: UIntType => a.copy(IntWidth(0))
	case a: SIntType => a.copy(IntWidth(0))
	case a: AggregateType => a.map(makeZero)
	}
	private def makeZeroWidth(tpe: ir.Type): ir.Type = tpe match {
	case ClockType => UIntType(IntWidth(0))
	case a: UIntType => a.copy(IntWidth(0))
	case a: SIntType => a.copy(IntWidth(0))
	case a: AggregateType => a.map(makeZeroWidth)
	}

I was about to link you to Utils.getGroundZero because that's the functionality that makeZero implies to me

[jackkoenig]

Well I'm too late, not worth changing heh