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Update spec to disallow 0-bit mux sel #2305
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Change the FIRRTL spec to disallow a zero-width multiplexer select. Clarify that the select line can be either one-bit or zero-bit, but will infer to one-bit. Signed-off-by: Schuyler Eldridge <[email protected]>
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Change the FIRRTL spec to disallow a zero-width multiplexer select. Clarify that the select line can be either one-bit or zero-bit, but will infer to one-bit. Signed-off-by: Schuyler Eldridge <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit ff1cd28) # Conflicts: # spec/spec.pdf # spec/spec.tex
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Change the FIRRTL spec to disallow a zero-width multiplexer select. Clarify that the select line can be either one-bit or zero-bit, but will infer to one-bit. Signed-off-by: Schuyler Eldridge <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit ff1cd28)
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Change the FIRRTL spec to disallow a zero-width multiplexer select. Clarify that the select line can be either one-bit or zero-bit, but will infer to one-bit. Signed-off-by: Schuyler Eldridge <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit ff1cd28) Co-authored-by: Schuyler Eldridge <[email protected]>
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Change the FIRRTL spec to disallow a zero-width multiplexer select.
Clarify that the select line can be either one-bit or zero-bit, but will
infer to one-bit.
This reverts language introduced in #2285 which did not match the Scala FIRRTL Compiler implementation around 0-bit select lines introduced in #2182.
For more discussion on the livelock that's been going on here, see: llvm/circt#1471 (comment).