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[mono][jit] Adding support for Vector128::ExtractMostSignificantBits intrinsic on ARM64 with miniJIT #84345
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ivanpovazan
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Apr 5, 2023
jandupej
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Apr 5, 2023
ivanpovazan
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WIP: [mono][jit] Adding support for Vector128::ExtractMostSignificantBits intrinsic on ARM64 with miniJIT
[mono][jit] Adding support for Vector128::ExtractMostSignificantBits intrinsic on ARM64 with miniJIT
Apr 5, 2023
ivanpovazan
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ivanpovazan
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vargaz,
lambdageek and
SamMonoRT
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April 5, 2023 17:51
vargaz
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Apr 12, 2023
…intrinsic on ARM64 miniJIT
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ivanpovazan
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ivanpovazan
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Overall, I would suggest removing most of the comments, as the code should be clear enough.
fanyang-mono
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Apr 14, 2023
Failures are unrelated and known:
tracked here: #84722
tracked here: #84434 |
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This PR adds support for
ExtractMostSignificantBits
intrinsic on ARM64 miniJIT.Implementation
On ARM64, there is no single instruction to perform the operation.
To emulate the behavior we implement a similar approach to coreCLR by performing the following set of operations:
byte
/sbyte
):byte
/sbyte
element types:New opcodes
Two new opcodes added:
OP_ARM64_USHL
- Shifts a vector left or right depending on the sign of the shift constant - USHL vectorOP_ARM64_EXT_IMM
- Extracts a vector from pair of vectors based on constant selector value - the lowest numbered byte element to be extracted in the range. EXT vectorOP_ARM64_EXT
which uses 3 source registers expecting the selector value to be in a register.Further optimizations
The current implementation can be further optimized. The following approaches could be examined:
ExtractMostSignificantBits
we generate inlined constants into the instruction stream.As the mask and shift constant are the same for a specific element type and can be reused, we could instead allocate them in a shared location to be reused between
ExtractMostSignificantBits
operations.Additionally, MSB masking could reuse the approach outlined here: [mono][jit] Adding support for Vector128::ExtractMostSignificantBits intrinsic on ARM64 with miniJIT #84345 (comment)
byte
andsbyte
element types we use 9 instructions to treat upper and lower half of the vector properly. This can be improved once we supportaddv.8b
as we would be able to just sum the lower 64bits of the source vector and not need to clear-out (ext with zero) the upper half of it before summing the full length. This would save us 1 instruction. Here is the summary of how currently the pseudo and generated code for the sequence looks like:Example:
Contributes to #76025
/cc: @jandupej @fanyang-mono