Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

file bACS_213.v modified #2

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

file bACS_213.v modified #2

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
101 changes: 59 additions & 42 deletions Vit_b213/src/bACS_213.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -34,48 +34,65 @@ module bACS_213 (acs_ppm_out, acs_Bx_out,
reg [`W-1:0] sumb;



always @(posedge clock or posedge reset)
begin
if (reset)
suma <=0;
else
begin
if (ae && acs_ppm_ina==4'b1111)
suma <= acs_ppm_ina;
else if (ae)
suma <= acs_ppm_ina + HD_ina;
end
end

always @(posedge clock or posedge reset)
begin
if (reset)
sumb <=0;
else
begin
if (ae && acs_ppm_inb ==4'b1111)
sumb <=acs_ppm_inb;
else if (ae)
sumb <= acs_ppm_inb + HD_inb;
end
end



always @(suma or sumb)
begin
if (suma <=sumb && ae)
begin
acs_ppm_out =suma;
acs_Bx_out =1'b0; //Select Upper Backward Path
end
else
begin
acs_ppm_out =sumb;
acs_Bx_out =1'b1; //Select Lower Backward Path
end
end
always @* begin
suma = acs_ppm_ina + HD_ina;
end
//always @(posedge clock or posedge reset)
// begin
// if (reset)
// suma <=0;
// else
// begin
// if (ae && acs_ppm_ina==4'b1111)
// suma <= acs_ppm_ina;
// else if (ae)
// suma <= acs_ppm_ina + HD_ina;
// end
// end

always @* begin
sumb = acs_ppm_inb + HD_inb;
end
//always @(posedge clock or posedge reset)
// begin
// if (reset)
// sumb <=0;
// else
// begin
// if (ae && acs_ppm_inb ==4'b1111)
// sumb <=acs_ppm_inb;
// else if (ae)
// sumb <= acs_ppm_inb + HD_inb;
// end
// end


always @(posedge clock or posedge reset) begin
if(reset)
{acs_ppm_out, acs_Bx_out} <= 0;
else begin
if(suma<=sumb && ae) begin
acs_ppm_out <= suma;
acs_Bx_out <= 1'b0;
end if(suma>=sumb && ae) begin
acs_ppm_out <= sumb;
acs_Bx_out <= 1'b1;
end
end
end
//always @(suma or sumb)
// begin
// if (suma <=sumb && ae)
// begin
// acs_ppm_out =suma;
// acs_Bx_out =1'b0; //Select Upper Backward Path
// end
// else
// begin
// acs_ppm_out =sumb;
// acs_Bx_out =1'b1; //Select Lower Backward Path
// end
// end



Expand Down