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[PowerPC] Use zext instead of anyext in custom and combine
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This custom combine currently converts an `and(anyext(x),c)`
into `anyext(and(x,c))`. This is not correct, because the original
expression guaranteed that the high bits are zero, while the new
one sets them to undef.

Emit `zext(and(x,c))` instead.

Fixes llvm#68783.
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nikic committed Oct 11, 2023
1 parent 0ead1fa commit c3b6edd
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Showing 2 changed files with 3 additions and 2 deletions.
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -15588,7 +15588,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
break;
SDValue ConstOp = DAG.getConstant(Imm, dl, MVT::i32);
SDValue NarrowAnd = DAG.getNode(ISD::AND, dl, MVT::i32, NarrowOp, ConstOp);
return DAG.getAnyExtOrTrunc(NarrowAnd, dl, N->getValueType(0));
return DAG.getZExtOrTrunc(NarrowAnd, dl, N->getValueType(0));
}
case ISD::SHL:
return combineSHL(N, DCI);
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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/PowerPC/and-extend-combine.ll
Original file line number Diff line number Diff line change
Expand Up @@ -23,11 +23,12 @@ bb:
ret ptr %i8
}

; FIXME: This is a miscompile.
define void @pr68783(i32 %x, ptr %p) {
; CHECK-LABEL: pr68783:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm r3, r3, 31, 24, 31
; CHECK-NEXT: li r5, 0
; CHECK-NEXT: sth r5, 4(r4)
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
%lshr = lshr i32 %x, 1
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