Do not forget to pass DWARF fragment information to LLVM. #115139
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I tried this on cargo release+debuginfo (per #115113 (comment)) and with LLVM assertions enabled, and it trips here: Actually, that does trigger once before your change too, at the very end on |
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| // CHECK: %slice.dbg.spill = alloca %Endian, | ||
| // CHECK: %s.dbg.spill = alloca { ptr, i64 }, | ||
| // CHECK: call void @llvm.dbg.declare(metadata ptr %s.dbg.spill, metadata ![[S:.*]], metadata !DIExpression()), | ||
| // CHECK: call void @llvm.dbg.declare(metadata ptr %slice.dbg.spill, metadata ![[SLICE:.*]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 0)), |
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Shouldn't this be something like 128, 0 rather than 0, 0?
It would probably be clearer to use a non-zero sized type here.
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Some changes occurred to MIR optimizations cc @rust-lang/wg-mir-opt |
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| pub fn extra(s: &[u8]) { | ||
| // CHECK: void @extra( | ||
| // CHECK: %slice.dbg.spill1 = alloca i32, | ||
| // CHECK: %slice.dbg.spill = alloca { ptr, i64 }, |
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Test should require 64-bit target, otherwise the sizes / offset aren't correct.
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☀️ Test successful - checks-actions |
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Finished benchmarking commit (f072775): comparison URL. Overall result: no relevant changes - no action needed@rustbot label: -perf-regression Instruction countThis benchmark run did not return any relevant results for this metric. Max RSS (memory usage)ResultsThis is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.
CyclesThis benchmark run did not return any relevant results for this metric. Binary sizeResultsThis is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.
Bootstrap: 630.812s -> 631.43s (0.10%) |
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I feel this patch can also be evaluated for a stable backport (if there will be plans for a 1.72.1 release). @rustbot label stable-nominated |
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Beta backport approved as per compiler team on Zulip. Stable backport declined (#115140 already disabled the MIR opt that caused fragment debuginfo to be generated from rustc, comment on Zulip). @rustbot label +beta-accepted -stable-nominated |
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[beta] backports - Contents of reachable statics is reachable rust-lang#115114 - Revert "Suggest using `Arc` on `!Send`/`!Sync` types" rust-lang#115311 - Stop emitting non-power-of-two vectors in (non-portable-SIMD) codegen rust-lang#115236 - Do not forget to pass DWARF fragment information to LLVM. rust-lang#115139 - rustdoc: use unicode-aware checks for redundant explicit link fastpath rust-lang#115070 r? cuviper
Represent MIR composite debuginfo as projections instead of aggregates
Composite debuginfo for MIR is currently represented as
```
debug name => Type { projection1 => place1, projection2 => place2 };
```
ie. a single `VarDebugInfo` object with that name, and its value a `VarDebugInfoContents::Composite`.
This PR proposes to reverse the representation to be
```
debug name.projection1 => place1;
debug name.projection2 => place2;
```
ie. multiple `VarDebugInfo` objects with each their projection.
This simplifies the handling of composite debuginfo by the compiler by avoiding weird nesting.
Based on rust-lang#115139
Fixes #115113 for the rustc part