Vivado block design changes #18
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No perfect solution for Verilog2001 - can't use localparam for module ports, so have to either change localparam to parameters or use expression in ports definition. Doing latter in this commit.
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@d953i - Requesting your review. |
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I already tried - works for me! |
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This branch is an attempt to fix the Vivado block design issue in #17 . To this end it is clearly insufficient, but it is placed here and proposed to see if it would work. Further changes can then be made to the rest of the repo.