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Vivado block design changes #18

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Vivado block design changes #18

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28f724b
Fix empty statement in sequential block warning
d953i Dec 11, 2019
39c8b7d
Use parameters for module ports
d953i Dec 12, 2019
50197a5
Create localparam_warning.png
d953i Dec 12, 2019
1850f8d
Delete localparam_warning.png
d953i Dec 12, 2019
9e29865
Merge branch 'master' into 39c8b7d0776ec6a1e68ee6a019096d93ab8505b0
ZipCPU Dec 14, 2019
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18 changes: 10 additions & 8 deletions rtl/wbm2axilite.v
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,11 @@
//
`default_nettype none
//
module wbm2axilite (
module wbm2axilite #(
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI R&W data
parameter C_AXI_ADDR_WIDTH = 28 // AXI Address width
) (

i_clk, i_reset,
// AXI write address channel signals
i_axi_awready, o_axi_awaddr, o_axi_awcache, o_axi_awprot, o_axi_awvalid,
Expand All @@ -58,10 +62,8 @@ module wbm2axilite (
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
o_wb_ack, o_wb_stall, o_wb_data, o_wb_err);

localparam C_AXI_DATA_WIDTH = 32;// Width of the AXI R&W data
parameter C_AXI_ADDR_WIDTH = 28;// AXI Address width
localparam DW = C_AXI_DATA_WIDTH;// Wishbone data width
parameter AW = C_AXI_ADDR_WIDTH-2;// WB addr width (log wordsize)
localparam AW = C_AXI_ADDR_WIDTH-2;// WB addr width (log wordsize)
input wire i_clk; // System clock
input wire i_reset;// Reset signal,drives AXI rst

Expand Down Expand Up @@ -100,12 +102,12 @@ module wbm2axilite (
input wire i_wb_cyc;
input wire i_wb_stb;
input wire i_wb_we;
input wire [(AW-1):0] i_wb_addr;
input wire [(DW-1):0] i_wb_data;
input wire [(DW/8-1):0] i_wb_sel;
input wire [(C_AXI_ADDR_WIDTH-3):0] i_wb_addr;
input wire [(C_AXI_DATA_WIDTH-1):0] i_wb_data;
input wire [(C_AXI_DATA_WIDTH/8-1):0] i_wb_sel;
output reg o_wb_ack;
output wire o_wb_stall;
output reg [(DW-1):0] o_wb_data;
output reg [(C_AXI_DATA_WIDTH-1):0] o_wb_data;
output reg o_wb_err;

//*****************************************************************************
Expand Down