This repository has been archived by the owner on Aug 20, 2024. It is now read-only.
Firrtl v1.4.3
Highlights
- Fix performance bug in RemoveAccesses (#2157)
Normally a bug fix would not be a highlight but this bug has been around for a very long time and could cause quadratic growth in FIRRTL runtime for expanding dynamic indexing of vecs of deeply nested aggregate type.
Feature
- Create annotation to allow inline readmem in Verilog (#2107)
- Add "Must Deduplicate" API (#2077)
- Add NoConstantPropagationAnnotation to disable constatnt propagation (#2150)
CLI option is--no-constant-propagation
- Add file line to source link in ScalaDoc (#2072)
Bug fixes
- Fix ProtoBuf conversions for Verification IR (#2100)
- Fix cat of zero-width SInt (#2116)
- Fix bug in zero-width memory removal (#2153)
- Legalize neg: -x becomes 0 - x (#2128)
- Ensure InlineCasts does not inline complex Expressions (#2130)
- Fix issue where inlined cvt could cause crash (#2124)
- Fix width of constant propagation of SInt with zero (#2120)
- Fix renaming in verilog prep (#1932)